• Journal of information and communication convergence engineering
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• 제2권2호
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• pp.93-96
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• 2004

The a-Si:H TFT using ferroelectric of $SrTiO_3$ as a gate insulator is fabricated on glass. Dielectric characteristics of ferroelectric are superior to $SiO_2$ and $Si_{3}N_{4}$. Ferroelectric increases on-current, decreases threshold voltage of TFT and also improves breakdown characteristics. The a-SiN:H has optical band gap of 2.61 eV, retractive index of 1.8∼2.0 and resistivity of $10^{13}$~$10^{15}$ $\Omega$cm, respectively. Insulating characteristics of ferroelectrics are excellent because dielectric constant of ferroelectric is about 60∼100 and breakdown strength is over 1MV/cm. TFT using ferroelectric has channel length of 8∼20 $\mu\textrm{m}$ and channel width of 80∼200 $\mu\textrm{m}$. And it shows that drain current is 3.4$\mu\textrm{A}$ at 20 gate voltage, $I_{on}$/$I_{off}$ is a ratio of $10^5$~$10^8$ and $V_{th}$ is 4∼5 volts, respectively. In the case of TFT without ferroelectric, it indicates that the drain current is 1.5 $\mu\textrm{A}$ at 20 gate voltage and $V_{th}$ is 5∼6 volts. With the improvement of the ferroelectric thin film properties, the performance of TFT using this ferroelectric has advanced as a gate insulator fabrication technology is realized.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.133-133
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• 2003

최근에 강유전체 매체와 원자력 현미경 (Atomic Force Microscopy, AFM)을 이용한 초고밀도 정보 저장 장치에 대한 연구가 활발히 진행되고 있다. 이와 아울러 나도 크기의 도메인에 대하 연구에 있어서 PZT 박막의 분극 방향에 따른 SrRuO$_3$의 저항 변화를 AFM 탐침을 이용하여 감지하는 방법을 제안하였다. 본 연구에서는 Metal tip/semiconductor/barrier oxide/ferroelectric 구조에서 강유전체 분극에 의한 저항 변화의 가능성을 실험하고자, 이와 등가 구조인 Pt tip/n-Si/SiO$_2$ 구조에서 Pt 탐침과 반도체 층 사이의 I-V 특성을 측정함으로써, 게이트 전압에 따른 반도체 층의 저항변화에 대해서 분석해 보았다. 그 결과 게이트 전압에 따라서 과밀 지역 (accumulation layer)과 공핍 지역 (depletion layer)이 형성됨에 따라서 반도체 층의 정항이 변하여 I-V 특성이 변하게 됨을 관찰하였으며, 이 결과로부터 분극 방향에 따라서도 반도체 층의 저항이 변할 수 있음을 알 수 있었다.

• 한국재료학회지
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• 제11권5호
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• pp.367-371
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• 2001

RF magnetron sputtering 법으로 T $a_2$ $O_{5}$ 세라믹 타겟과 S $r_2$N $b_2$ $O_{7}$ 세라믹 타겟을 동시 sputtering하여 저유전율 S $r_2$(T $a_{1-x}$ , N $b_{x}$)$_2$ $O_{7}$(STNO) 박막을 p-type Si (100) 기판 위에 증착하여 NDRO 강유전체 메모리 (Non-destructive read out ferro-electric random access memory)에 사용되는 Pt/STNO/Si (MFS) 구조의 응용 가능성을 확인하였다. Sr$_2$Nb$_2$ $O_{7} (SN O)$ 타겟과 T $a_2$ $O_{5}$ 타겟의 출력의 비를 100w/100w, 70w/100w, 그리고 50w/100w로 조절하면서 x 값을 달리하여 조성을 변화시켰다. 성장된 박막을 8$50^{\circ}C$, 90$0^{\circ}C$, 그리고 9$50^{\circ}C$에서 1시간 동안 산소 분위기에서 열처리하였다. 조성과 열처리 온도에 따른 구조적 특징을 XRD에 의해 관찰하였으며 표면특성은 FE-SBM에 의해 관찰하였고, C-V 측정과 I-V 측정으로 박막의 전기적 특성을 조사하였다. SNO 타겟과 T $a_2$ $O_{5}$ 타켓의 출력비에 따른 STNO 박막의 성장 결과 70W/170W의 출력비에서 성장된 STNO박막에서 Ta의 양이 상대적 맡은 x=0.4였으며 가장 우수한 C-V 특성 및 누설 전류 특성을 보였다. 이 조성에서 성장된 STNO박막은 3-9V외 인가전압에서 메모리 윈도우 갑이 0.5-8.3V였고 누설전류밀도는 -6V의 인가전압에서 7.9$\times$10$_{-8}$A /$\textrm{cm}^2$였다.

• 반도체디스플레이기술학회지
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• 제6권3호
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• pp.41-45
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• 2007

The (SrCa)$TiO_3$(SCT) thin films were deposited on Pt-coated electrode(Pt/TiN/$SiO_2$/Si) using RF sputtering method according to the deposition condition. The crystallinity of SCT thin films were increased with increase of deposition temperature in the temperature range of $100{\sim}500[^{\circ}C]$. The optimum conditions of RF power and Ar/$O_2$ ratio were 140[W] and 80/20, respectively. Deposition rate of SCT thin films was about $18.75[{\AA}/min]$ at the optimum condition. The composition of SCT thin films deposited on Si substrate is close to stoichiometry (1.081 in A/B ratio). The maximum dielectric constant of SCT thin film was obtained by annealing at $600[^{\circ}C]$.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권12호
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• pp.576-580
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• 2006

The $(Sr_{0.85}Ca_{0.15})TiO_3(SCT)$ thin films were deposited on Pt-coated electrode $(Pt/TiN/SiO_2/Si)$ using RF sputtering method according to the deposition condition. The crystallinity of SCT thin films were increased with increase of deposition temperature in the temperature range of $100{\sim}500[^{\circ}C]$. The optimum conditions of RF power and $Ar/O_2$ ratio were 140[W] and 80/20, respectively. Deposition rate of SCT thin films was about $18.75[{\AA}/min]$ at the optimum condition. The composition of SCT thin films deposited on Si substrate is close to stoichiometry (1.102 in A/B ratio). The maximum dielectric constant of SCT thin film as obtained by annealing at $600^{\circ}C$.

• E2M - 전기 전자와 첨단 소재
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• 제16권9호
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• pp.64.1-64
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• 2003

A metal-ferroelectric [SrBi$_2$Ta$_2$O$\_$9/ (SBT)-high-k-insulator(PrOx)-semiconductor(Si) structure has been fabricated and evaluated as a key part of metal-ferroelectric-insulator-semiconductor-field-effect-transistor MFIS-FET memory, aiming to improve the memory retention characteristics by increasing the dielectric constant in the insulator layer and suppressing the depolarization field in the SBT layer. A 20-nm PrOx film grown on Si(100) showed both a high of about 12 and a low leakage current density of less than 1${\times}$ 10e-8 A/$\textrm{cm}^2$ at 105 MV/cm. A 400-nm SBT film prepared on PrOx/Si shows a preferentially oriented (105) crystalline structure, grain size of about 130 nm and subface roughness of 3.2 nm. A capacitance-voltage hysteresis is confirmed on the Pt/SBT/PrOx/Si diode with a memory window of 0.3V at a sweep voltage width of 12 V. The memory retention time was about 1 104s, comparable to the conventional Pt/SBT/SiO$\_$x/N$\_$y/(SiO$\_$N/)/Si. The gradual change of the capacitance indicates that some memory degradation mechanism is different from that in the Pt/SBT/SiON/Si structure.

• 한국전기전자재료학회논문지
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• 제11권11호
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• pp.984-989
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• 1998

The ($Sr_{1-x}Ca_x)TiO_3$(SCT) thin films are deposited on Pt-coated electrode($Pt/TiN/SiO_2/Si$) using RF sputtering method with substitutional contents of Ca. The maximum grain of thin films is obtained by substitution of Ca at 15[mol%]. All SCT thin films had (111) preferred orientation. The dielectric constant was increased with increasing the substitutional contents of Ca, while it was decreased if the substitutional contents of Ca exceeded over 15[mol%]. The dielectric constant changes almost linearly in temperature ranges of -80~+90[$^{\circ}C$]. The temperature properties of the dielectric loss have a stable value within 0.02 independent of the substitutional contents of Ca. All SCT thin films used in this study show the phenomena of dielectric relaxation with the increase of frequency, and the relaxation frequency is observed above 200[kHz].

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.1001-1004
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• 2001

The (Sr$_{l-x}$Ca$_{x}$)TiO$_3$(SCT) thin films are deposited on Pt-coated electrode(Pt/TiN/SiO$_2$/Si) using RF sputtering method with substitutional contents of Ca. The maximum grain of thin films is obtained by substitution of Ca at 15[mol%]. The dielectric constant was increased -with increasing the substitutional contents of Ca, while it was decreased if the substitutional contents of Ca exceeded over 15[mol%]. The dielectric constant changes almost linearly in temperature ranges of -80~+90[$^{\circ}C$]. The temperature properties of the dielectric loss have a stable value within 0.02 independent of the substitutional contents of Ca. The current-voltage characteristics of SCT15 thin films showed the increasing leakage current as the measuring temperature increases.ses.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.240-243
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• 1999

(Sr$\sub$0.85/Ca$\sub$0.15/)TiO$_3$thin films were deposited on Pt-coated TiO$_2$/SiO$_2$/Si wafer by the rf sputtering method. Experiments were conducted to investigate the electrical properties of SCT thin films with various top electrode. C-F and C-V measurements show that SCT thin films annnealed at 600$^{\circ}C$ have a larger capacitance than SCT thin films deposited at 400$^{\circ}C$ , and there is nearly no difference between top electrodes. I-V measurement show that Pt top electrode have a good leakage current density of < 10nA/$\textrm{cm}^2$,. making them suitable for DRAM application.