• Title/Summary/Keyword: $SiO_2$ layer

Search Result 1,763, Processing Time 0.033 seconds

Groundwater Ages and Flow Paths at a Coastal Waste Repository Site in Korea, Based on Geochemical Characteristics and Numerical Modeling

  • Cheong, Jae-Yeol;Hamm, Se-Yeong;Koh, Dong-Chan;Lee, Chung-Mo;Ryu, Sang Min;Lee, Soo-Hyoung
    • The Journal of Engineering Geology
    • /
    • v.26 no.1
    • /
    • pp.1-13
    • /
    • 2016
  • Groundwater flow paths and groundwater ages at a radioactive waste repository located in a coastal area of South Korea were evaluated using the hydrochemical and hydrogeological characteristics of groundwater, surface water, rain water, and seawater, as well as by numerical modeling. The average groundwater travel time in the top layer of the model, evaluated by numerical modeling and groundwater age (34 years), approximately corresponds to the groundwater age obtained by chlorofluorocarbon (CFC)-12 analysis (26-34 years). The data suggest that the groundwater in wells in the study area originated up-gradient at distances of 140-230 m. Results of CFC analyses, along with seasonal variations in the δ18O and δD values of groundwater and the relationships between 222Rn concentrations and δ18O values and between 222Rn concentrations and δD values, indicate that groundwater recharge occurs in the summer rainy season and discharge occurs in the winter dry season. Additionally, a linear relationship between dissolved SiO2 concentrations and groundwater ages indicates that natural mineralization is affected by the dilution of groundwater recharge in the rainy summer season.

High Voltage β-Ga2O3 Power Metal-Oxide-Semiconductor Field-Effect Transistors (고전압 β-산화갈륨(β-Ga2O3) 전력 MOSFETs)

  • Mun, Jae-Kyoung;Cho, Kyujun;Chang, Woojin;Lee, Hyungseok;Bae, Sungbum;Kim, Jeongjin;Sung, Hokun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.32 no.3
    • /
    • pp.201-206
    • /
    • 2019
  • This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

Characteristics of a planar Bi-Sb multijunction thermal converter with Pt-heater (백금 히터가 내장된 평면형 Bi-Sb 다중접합 열전변환기의 특성)

  • Lee, H.C.;Kim, J.S.;Ham, S.H.;Lee, J.H.;Lee, J.H.;Park, S.I.;Kwon, S.W.
    • Journal of Sensor Science and Technology
    • /
    • v.7 no.3
    • /
    • pp.154-162
    • /
    • 1998
  • A planar Bi-Sb multijunction thermal converter with high thermal sensitivity and small ac-dc transfer error has been fabricated by preparing the bifilar thin film Pt-heater and the hot junctions of thin film Bi-Sb thermopile on the $Si_{3}N_{4}/SiO_{2}/Si_{3}N_{4}$-diaphragm, which functions as a thermal isolation layer, and the cold junctions on the dielectric membrane supported with the Si-substrate, which acts as a heat sink, and its ac-dc transfer characteristics were investigated with the fast reversed dc method. The respective thermal sensitivities of the converter with single bifilar heater were about 10.1 mV/mW and 14.8 mV/mW in the air and vacuum, and those of the converter with dual bifilar heater were about 5.1 mV/mW and 7.6 mV/mW, and about 5.3 mV/mW and 7.8 mV/mW in the air and vacuum for the inputs of inside and outside heaters, indicating that the thermal sensitivities in the vacuum, where there is rarely thermal loss caused by gas, are higher than those in the air. The ac-dc voltage and current transfer difference ranges of the converter with single bifilar heater were about ${\pm}1.80\;ppm$ and ${\pm}0.58\;ppm$, and those of the converter with dual bifilar heater were about ${\pm}0.63\;ppm$ and ${\pm}0.25\;ppm$, and about ${\pm}0.53\;ppm$ and ${\pm}0.27\;ppm$, respectively, for the inputs of inside and outside heaters, in the frequency range below 10 kHz and in the air.

  • PDF

The Film Property and Deposition Process of TSV Inside for 3D Interconnection (3D Interconnection을 위한 실리콘 관통 전극 내부의 절연막 증착 공정과 그 막의 특성에 관한 연구)

  • Seo, Sang-Woon;Kim, Gu-Sung
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.15 no.3
    • /
    • pp.47-52
    • /
    • 2008
  • This investigation was performed in order to study the properties of deposition and layers by Silicon Dioxide, SiO2, as dielectric onto Via and Trench which have high Aspect Ratio (AR). Thus, in order to confirm these properties, three types of CVD, which were PECVD, PETEOS, and ALD, were selected. On the experiment each of the property sections was estimated that step overage of PECVD: <30%, PETEOS: 45%, ALD: 75% and the RSM of PECVD: 27.8 nm, PETEOS: 2.1 nm, ALD: <2.0 nm. As a result of this experiment for the property of electric film, ALD was valuated to be the most favorable outcome. However, ALD was valuated to have the least quality for the deposition rate. ALD deposition rate, $10\;\AA/min$ by $1\;\AA$/1cycle, was prominently lower than PETEOS, which had the deposition rate of $5000\;\AA$/min. Since electric film requires at least $1000\;\AA$ thicknesses, ALD was not suitable for the deposition rate. which is the most important component in a practical use. Therefore, in this particular study, PETEOS was evaluated to be the most suitable recipe.

  • PDF

A Study on Anisotropic Compression Behavior of Illite (일라이트의 비등방적 압축특성 연구)

  • Yun, Seohee;Lee, Yongjae
    • Korean Journal of Mineralogy and Petrology
    • /
    • v.33 no.1
    • /
    • pp.11-18
    • /
    • 2020
  • High-pressure synchrotron X-ray powder diffraction experiments were performed on natural illite (K0.65Al2(Al0.65Si3.35)O10(OH)2) using diamond anvil cell (DAC) under two different pressure transmitting media (PTM), i.e., water and ME41 (methanol:ethanol = 4:1 by volume). When using water as PTM, occasional heating was applied up to about 250℃ while reaching pressure up to 2.7 GPa in order to promote both hydrostatic conditions and intercalation of water molecules into the layer. When using ME41, pressure was reached up to 6.9 GPa at room temperature. Under these conditions, illite did not show any expansion of interlayer distance or phase transitions. Pressure-volume data were used to derive bulk moduli (K0) of 45(3) GPa under water and 51(3) GPa under ME41 PTM. indicating no difference in compressibility within the analytical error. Linear compressibilities were then calculated to be βa = 0.0025, βb = 0.0029, βc = 0.0144 under ME41 PTM showing the c-axis is ca. six times more compressible than a- and b-axes. These elastic behaviors of illite were compared to muscovite, one of its structural analogues.

Fabrication of Triode Type Field Emission Device Using Carbon Nanotubes Synthesized by Thermal Chemical Vapor Deposition (열 화학 기상 증착법을 이용한 삼극관 구조의 탄소 나노 튜브 전계 방출 소자의 제조)

  • Yu W. J.;Cho Y. S.;Choi G. S.;Kim D. J.
    • Korean Journal of Materials Research
    • /
    • v.14 no.8
    • /
    • pp.542-546
    • /
    • 2004
  • We report a new fabrication process for high performance triode type CNT field emitters and their superior electrical properties. The CNT-based triode-type field emitter structure was fabricated by the conventional semiconductor processes. The keys of the fabrication process are spin-on-glass coating and trim-and-leveling of the carbon nanotubes grown in trench structures by employing a chemical mechanical polishing process. They lead to strong adhesion and a uniform distance from the carbon nanotube tips to the electrode. The measured emission property of the arrays showed a remarkably uniform and high current density. The gate leakage current could be remarkably reduced by coating of thin $SiO_{2}$ insulating layer over the gate metal. The field enhancement factor(${\beta}$) and emission area(${\alpha}$) were calculated from the F-N plot. This process can be applicable to fabrication of high power CNT vacuum transistors with good electrical performance.

Single layer antireflection coating on PET substrates for display applications

  • Gowtham, M.;Mangalaraj, D.;Seo, Chang-Ki;Shim, Myung-Suk;Hwang, Sun-Woo;Yi, Jun-Sin
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 2004.08a
    • /
    • pp.988-991
    • /
    • 2004
  • In the present investigation, we tried AR coating simulation by using the "Essential Macleod optical coating design and analysis" program. After various run of the program we selected appropriate materials which have specific refractive indices and for that thickness was optimized to get the low reflectance. By comparing the simulated results for the different materials,we found that $SiO_2$ and TiN are the appropriate materials for this Flat panel device (FPD) application. Thin films of these materials were deposited using RF magnetron sputtering and Inductively Coupled Plasma Chemical Vapour Deposition (ICPCVD) methods on Polyethyleneterephthalate (PET) substrates. Spectroscopic ellipsometer (SE MF-1000) and UV-Vis spectrophotometer (SCINCO) were used for the optical characterization. The obtained experimental results are in good agreement with the simulation results.

  • PDF

플라즈마 전해산화 공정에 있어서 전해액 내 실리콘 이온이 표면특성에 미치는 영향

  • Kim, Seong-Cheol;Yun, Sang-Hui;Seong, Gi-Hun;Gang, Du-Hong;Min, Gwan-Sik;Cha, Deok-Jun;Kim, Jin-Tae;Yun, Ju-Yeong
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2013.02a
    • /
    • pp.290-290
    • /
    • 2013
  • 플라즈마 전해산화(Plasma Electrolytic Oxidation)란 저 농도의 알칼리 전해액을 매개로, 고전압을 가해 미세 플라즈마 방전을 유도하여 Al, Mg, Ti 등의 금속표면을 산화시켜 고내식성, 초경합금 수준의 내마모성, 탁월한 절연성과 고경도성을 가지는 산화막을 형성시키는 기술로 전자, 자동차, 의료, 섬유, 해양, 석유화학 산업에 이르기까지 광범위한 분야에 적용되어 우수한 물성을 확보할 수 있는 차세대의 표면처리 기술이다. 본 연구에서는 6061 알루미늄 합금을 이용하여 다양한 전해액 조건에서 플라즈마 전해산화 공정으로 Al2O3 산화막을 형성시켰다. 산화막의 조성 및 미세구조는 XRD와 FE-SEM, EDS를 이용하여 분석하였다. 형성된 산화막은 회색에서 밝은 회색으로 시편 전면에 고르게 나타났다. 전해액 조성을 바꾸어줌에 따라 각기 다른 표면 특성을 가지는 산화막을 얻을 수 있었고, 그에 따른 물성 변화를 분석하였다. 특히 Si 이온 농도를 조절함으로써 피막 성장인자와 표면 미세구조를 제어할 수 있었다.

  • PDF

Comparative Study of Celadon Shards from Gangjin and Buan Kiln Sites (강진과 부안 청자 도편의 비교연구)

  • No, Hyunggoo;Kim, Soomin;Kim, Ungsoo;Cho, Wooseok;Han, Junghwa
    • Journal of the Korean Ceramic Society
    • /
    • v.52 no.1
    • /
    • pp.41-47
    • /
    • 2015
  • Celadon shards from Gangjin and Buan were analyzed for their color, chemistry and microstructures. They exhibited similar chromatic characteristics in a $CIEL^*a^*b^*$ analysis. All of the glazes assessed showed comparable compositional areas, while the bodies from Gangjin shards had higher $RO_2$ concentrations. A high degree of similarity was also noted in the microstructures of the glaze and bodies from both regions. Anorthite crystals appeared in the glaze layer, and phase separation behavior developed around these crystals. This may have been caused by the glaze chemistry and the sintering process given the lengthy heating and cooling time. A Raman analysis indicated higher isolated $SiO_4$ unit ($Q_0$) values for the Buan samples. This can stem from the higher firing temperature or the longer sintering process.

Device and Circuit Performance Issues with Deeply Scaled High-K MOS Transistors

  • Rao, V. Ramgopal;Mohapatra, Nihar R.
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.4 no.1
    • /
    • pp.52-62
    • /
    • 2004
  • In this paper we look at the effect of Fringe-Enhanced-Barrier-lowering (FEBL) for high-K dielectric MOSFETs and the dependence of FEBL on various technological parameters (spacer dielectrics, overlap length, dielectric stack, S/D junction depth and dielectric thickness). We show that FEBL needs to be contained in order to maintain the performance advantage with scaled high-K dielectric MOSFETs. The degradation in high-K dielectric MOSFETs is also identified as due to the additional coupling between the drain-to-source that occurs through the gate insulator, when the gate dielectric constant is significantly higher than the silicon dielectric constant. The technology parameters required to minimize the coupling through the high-K dielectric are identified. It is also shown that gate dielectric stack with a low-K material as bottom layer (very thin $SiO_2$ or oxy-nitride) will be helpful in minimizing FEBL. The circuit performance issues with high-K MOS transistors are also analyzed in this paper. An optimum range of values for the dielectric constant has been identified from the delay and the energy dissipation point of view. The dependence of the optimum K for different technology generations has been discussed. Circuit models for the parasitic capacitances in high-K transistors, by incorporating the fringing effects, have been presented.