• JSTS:Journal of Semiconductor Technology and Science
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• 제1권2호
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• pp.95-102
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• 2001

Hafnium oxide thin films for gate dielectric were deposited at $300^{\circ}C$ on p-type Si (100) substrates by plasma enhanced chemical vapor deposition (PECVD) and annealed in $O_2$ and $N_2$ ambient at various temperatures. The effect of hydrogen treatment in 4% $H_2$ at $350^{\circ}C$ for 30 min on the electrical properties of $HfO_2$for gate dielectric was investigated. The flat-band voltage shifts of $HfO_2$capacitors annealed in $O_2$ambient are larger than those in $N_2$ambient because samples annealed in high oxygen partial pressure produces the effective negative charges in films. The oxygen loss in $HfO_2$films was expected in forming gas annealed samples and decreased the excessive oxygen contents in films as-deposited and annealed in $O_2$ or $N_2$ambient. The CET of films after hydrogen forming gas anneal almost did not vary compared with that before hydrogen gas anneal. Hysteresis of $HfO_2$films abruptly decreased by hydrogen forming gas anneal because hysteresis in C-V characteristics depends on the bulk effect rather than $HfO_2$/Si interface. The lower trap densities of films annealed in $O_2$ambient than those in $N_2$were due to the composition of interfacial layer becoming closer to $SiO_2$with increasing oxygen partial pressure. Hydrogen forming gas anneal at $350^{\circ}C$ for samples annealed at various temperatures in $O_2$and $N_2$ambient plays critical role in decreasing interface trap densities at the Si/$SiO_2$ interface. However, effect of forming gas anneal was almost disappeared for samples annealed at high temperature (about $800^{\circ}C$) in $O_2$ or $N_2$ambient.

• 한국재료학회지
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• 제12권6호
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• pp.508-512
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• 2002

$2000{\AA}-SiO_2/Si(100)$ and $560{\AA}-Si_3N_4/Si(100)$ wafers, which are 10 cm in diameter, were directly bonded using a rapid thermal annealing method. We fixed the anneal time of 30 second and varied the anneal temperatures from 600 to $1200^{\circ}C$. The bond strength of bonded wafer pairs at given anneal temperature were evaluated by a razor blade crack opening method and a four-point bonding method, respectively. The results clearly slow that the four-point bending method is more suitable for evaluating the small bond strength of 80~430 mJ/$\m^2$ compared to the razor blade crack opening method, which shows no anneal temperature dependence in small bond strength.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.157-158
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• 2007

Effects of post-metallization anneal (PMA) on interface trap characteristics of Si-$SiO_2$ are studied. The conventional PMA method utilizes forming gas anneal, where 10% hydrogen in nitrogen atmosphere is used. A new PMA method utilizes hydrogen rich PECVD- silicon nitride $(SiN_x)$ film as a hydrogen diffusion source and a out-diffusion blocking layer. It can be shown through charge pumping current measurement that the new PMA is indeed effective to decrease Si-$SiO_2$ interface trap density.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1993년도 춘계학술발표회
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• pp.22-22
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• 1993

Tungsten silicide는 낮은 전도도, 높은 녹는점, pattern 형성에 용이함등으로 VLSI device Interconnect(Bit line)로 활발하게 이용되고 있다. 일반적으로 Tungsten silicide 는 polycide(WSi$_2$/poly-Si)구조로 사용이 되며, polycide 구조는 산화분위기에서 WSi$_2$위에 SiO$_2$막을 쉽게 형성시키는 장점이 있다. As-dep상태의 polycide를 산화시킬적에는 텅스텐 실리사이드에 존재하는 excess-silicon과 microcrystalline 구조 (grain size=3$\AA$)로 인하여 텅스텐 실리사이드 표면에 균일한 SiO$_2$가 형성이 된다. 그러나 post-anneal을 실시한 샘플 Furnace anneal ($N_2$:O$_2$유량비=2:1) 처리하면 성장된 텅스텐 실사이드 입자의 입계효과에 의하여 텅스텐 실리사이드의 표면에 SiO$_2$뿐만 아니라 WO$_3$가 형성되는 이상산화가 발생되어 공정의 어려움을 야기시키고 있다. 본 실험에서는 post anneal ($700^{\circ}C$, 30min, $N_2$ 분위기) 시킨 시편을 Implantation(As 또는 phosphorous)을 실시하여 실리사이드 표면을 비정질화 시킨후 Furnace anneal 실시하여 이상산화 발생 억제에 I/I처리가 미치는 효과를 관찰하였다. XPS를 이용하여 이상산화막 두께와 WO$_3$존재를 조사하였고, AES를 사용하여 W, Si, O 원소들이 깊이에 따라 변하는 것을 관찰하였다.

• 한국진공학회지
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• 제17권3호
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• pp.199-203
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• 2008

$O_2$ 플라즈마를 이용한 표면처리 공정이 Bio-FET (biologically sensitive field-effect transistor)에 미치는 영향을 조사하기 위하여, SOI (Silicon-on-Insulator) wafer와 sSOI (strained- Si-on-Insulator) wafer를 이용하여 pseudo-MOSFET을 제작하고 $O_2$ 플라즈마를 이용하여 표면처리를 진행하였다. 제작된 시료들은 back gated metal contact junction 방식으로 측정되었다. $I_D-V_G$ 특성과 field effect mobility 특성의 관찰을 통하여 $O_2$ 플라즈마 표면처리에 따른 각 시료들의 전기적 특성 변화에 대하여 관찰하였다. 그리고 $O_2$ 플라즈마 표면처리 과정에서 플라즈마에 의한 손상을 받은 시료들은 2% 수소희석가스 ($H_2/N_2$)를 이용한 후속 열처리 공정을 진행한 후 전기적 특성이 향상되는 것을 관찰할 수 있었다. 이는 수소희석가스를 이용한 후속 열처리 공정을 통하여 산화막과 Si 사이의 계면 준위와 산화막 내부의 전하 포획 준위를 감소시켰기 때문이다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 추계학술대회 논문집
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• pp.9-12
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• 1998

Film characteristics of thin reoxidized nitrided oxides were investigated by SIMS analysis and C-V method in order to use the gate dielectric for charge-trap type NVSMs instead of ONO stacked layers. Nitric oxide(NO) annealed film has the nitrogen content sharply peaked at the Si-SiO$_2$ interface, while it is broad for nitrous oxide($N_2$O) ambient. The nitrogen peak concentration increased with anneal temperature and time. The position of nitrogen content in the oxide layer was due to be precisely controlled. For the films annealed NO ambient at 80$0^{\circ}C$ for 30min. followed by reoxidized at 85$0^{\circ}C$, the maximum memory window of 3.5V was obtained and the program condition was +12V, 1msec for write and -l3V, 1msec for erase.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.180-184
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• 2002

In this paper, the electrical properties of PVD Ta and $TaN_x$ gate electrodes on $SiO_2$ and their thermal stabilities are investigated. The results show that the work functions of $TaN_x$ gate electrode are modified by the amount of N, which is controlled by the flow rate of $N_2$during reactive sputtering process. The thermal stability of Ta and $TaN_x$ with RTO-grown $SiO_2$ gate dielectrics is examined by changes in equivalent oxide thickness (EOT), flat-band voltage ($V_{FB}$), and leakage current after post-metallization anneal at high temperature in $N_2$ambient. For a Ta gate electrode, the observed decrease in EOT and leakage current is due to the formation of a Ta-incorporated high-K layer during the high temperature annealing. Less change in EOT and leakage current is observed for $TaN_x$ gate electrode. It is also shown that the frequency dispersion and hysteresis of high frequency CV curves are improved significantly by a post-metallization anneal.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.37-40
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• 1999

For the first time, charge trapping nonvolatile semiconductor memories with the deoxidized oxynitride gate dielectric is proposed and demonstrated. Gate dielectric wit thickness of less than 1 nm have been grown by postnitridation of pregrown thermal silicon oxides in NO ambient and then reoxidation. The nitrogen distribution and chemical state due to NO anneal/reoxidation were investigated by M-SIMS, TOF-SIMS, AES depth profiles. When the NO anneal oxynitride film was reoxidized on the nitride film, the nitrogen at initial oxide interface not only moved toward initial oxide interface, but also diffused through the newly formed tunnel oxide by exchange for oxygen. The results of reoxidized oxynitride(ONO) film analysis exhibits that it is made up of SiO$_2$(blocking oxide)/N-rich SiON interface/Si-rich SiON(nitrogen diffused tunnel oxide)/Si substrate. In addition, the SiON and the S1$_2$NO Phase is distributed mainly near the tunnel oxide, and SiN phase is distributed mainly at tunnel oxide/Si substrate interface.

• 대한전기학회논문지
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• 제45권2호
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• pp.242-248
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• 1996

The properties of TiN/TiSi$_{2}$ bilayer formed by a rapid thermal annealing is investigated when thin SiO$_{2}$ film exists at the Ti-Si interface. The competitive reaction for the TiN/TiSi_2 bilayer occurs above 600 .deg. C. The thickness of the TiSi$_{2}$ layer decreases with increasing SiO$_{2}$ film thickness and also decreases with increasing anneal temperture When the competitive reaction for the TiN/TiSi$_{2}$ bilayer is occured by rapid thermal annealing, the composition of TiN layer represents TiN$_{x}$O$_{y}$ due to the SiO$_{2}$ layer at the Ti-Si interface but the structures of the TiN and TiSi$_{2}$ layers were not changed.d.d.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 C
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• pp.1223-1225
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• 1994

The properties of $TiN/TiSi_2$ bilayer formed by a rapid thermal anneal ing is investigated when thin $SiO_2$ film exists at the Ti-Si interface. The competitive reaction for the $TiN/TiSi_2$ bilayer occurs above $600^{\circ}C$. The thickness of the $TiSi_2$ layer decreases with increasing $SiO_2$ film thickness while the TiN layer increases at the competitive reaction. The composition of TiN layer is changed to the $TiN_xO_y$ film due to the thin $SiO_2$ layer at the Ti-Si interface while the structure of the TiN and $TiSi_2$ layers was not changed.