• 한국자기학회지
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• 제9권3호
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• pp.136-142
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• 1999

Ni0.65Zn0.35Cu0.3Fe1.7O4의 결정학적 및 자기적 성질을 X-선 회절법과 Mossbauer 분광법, 진동시료 자화율 측정기(VSM)로 연구하였다. 결정구조는 cubic spinel 구조이며, 격자상수 a0=8.403$\AA$임을 알았다. Mossbauer 스펙트럼은 12K부터 665K까지 취하였으며, 온도가 상승함에 따라 Mossbauer 스펙트럼의 line broadening 현상이 나타났다. 이는 철의 자리에서 여러 다른 초미세자기장의 온도의존성으로부터 기인된다고 볼 수 있고, 분포함수 모델을 사용하여 실온에서 사면체자리[A자리], 팔면체자리[B자리]의 초미세자기장값 Hhf(A)=470kOe, Hhf(B0)=495kOe, Hhf(B1)=485kOe, Hhf(B2)=453kOe, Hhf(B3)=424kOe, Hhf(B4)=390kOe, Hhf(Bavr.)=451kOe을 얻었다. 실온에서 이성질체 이동결과 A, B자리 모두 Fe+3임을 알았고, Neel 온도 TN=665K로 결정하였다. VSM 실험결과 실온에서 포화자화값은 66emu/g이고 보자력은 36Oe를 나타냈다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2005년도 제28회 학술발표회 초록집
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• pp.61-61
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• 2005

• 한국진공학회:학술대회논문집
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• 한국진공학회 2003년도 제24회 학술발표회 초록집
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• pp.199-199
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• 2003

• 한국세라믹학회지
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• 제49권4호
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• pp.333-336
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• 2012

The study to give electrical conductivity by dispersing carbon nanotubes (CNT) into silicon nitride ($Si_3N_4$) ceramics has been carried out in recent years. However, the density and the strength of $Si_3N_4$ ceramics were degraded and CNTs disappeared after firing at high temperatures because CNTs prevent $Si_3N_4$ from densification and there is a possibility that CNTs react with $Si_3N_4$ or $SiO_2$. In order to suppress the reaction and the disappearance of CNTs, lower temperature densification is needed. In this study, $HfO_2$ and $TiO_2$ was added to $Si_3N_4-Y_2O_3-Al_2O_3$-AlN system to fabricate CNT-dispersed $Si_3N_4$ ceramics at lower temperatures. $HfO_2$ promotes the densification of $Si_3N_4$ and prevents CNT from disappearance. As a result, the sample by adding $HfO_2$ and $TiO_2$ fired at lower temperatures showed higher electrical conductivity and higher bending strength. It was also shown that the mechanical and electrical properties depended on the quantity of the added CNTs.

• 한국전기전자재료학회논문지
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• 제36권3호
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• pp.298-302
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• 2023

In this paper, we discussed the effect of field plate dielectric materials such as silicon dioxide (SiO₂), aluminum oxide (Al₂O₃), and hafnium oxide (HfO₂) on the breakdown characteristics of β-Ga₂O₃ Schottky barrier diodes (SBDs). The breakdown voltage (BV) of the SBDs with a field plate was higher than that of SBDs without a field plate. The higher dielectric constant of HfO₂ contributed to the superior reduction in electric field concentration at the Schottky junction edge from 5.4 to 2.4 MV/cm. The SBDs with HfO₂ field plate showed the highest BV of 720 V, and constant specific on-resistance (R_on,sp) of 5.6 mΩ·cm², resulting in the highest Baliga's figure-of-merit (BFOM) of 92.0 MW/cm². We also investigated the effect of dielectric thickness and field plate length on BV.

• 한국전기전자재료학회논문지
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• 제25권1호
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• pp.1-5
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• 2012

In this paper, matching characteristic of MIM (metal-insulator-metal) capacitor with $Al_2O_3/HfO_2/Al_2O_3$ (AHA) structure is analyzed. The floating gate capacitance measurement technique (FGMT) was used for analysis of matching characteristic of the MIM capacitors in depth. It was shown that matching coefficient of AHA MIM capacitor is 0.331%${\mu}m$ which is appropriate for application to analog/RF integrated circuits. It was also shown that the matching coefficient has a more strong dependence on the width than length of MIM capacitor.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.152-153
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• 2012

Ion sensitive field effect transistor (ISFET)는 전해질 속 각종 이온농도를 측정하는 반도체 이온 센서이다. 이 소자의 기본 구조는 metal oxide semiconductor field effect transistor (MOSFET)에서 고안되었으며 게이트 컨택 부분이 기준전극과 전해질로 대체되어진 구조를 가지고 있다 [1]. ISFET는 기존의 반도체 CMOS 공정과 호환이 가능하고 제작이 용이할 뿐만 아니라, pH용액에 대한 빠른 반응 속도, 비표지 방식의 생체물질 감지능력, 낮은 단가 및 소자의 집적이 용이하다는 장점을 가지고 있다. ISFET pH센서의 감지특성에 결정하는 요소 중 가장 중요한 것은 소자의 감지막이라고 할 수 있다. 감지막은 감지 대상 물질과 물리적으로 직접 접촉되는 부분으로서 일반적으로 기계적/화학적 강도가 우수한 실리콘 산화막(SiO2)이 많이 사용되어져 왔다. 최근에는 기존의 SiO2 보다 성능이 향상된 감지막을 개발하기 위하여 Al2O3, HfO2, ZrO2, 그리고 Ta2O5와 같은 고유전 상수(high-k)를 가지는 물질들을 EIS 센서의 감지막으로 이용하는 연구가 활발하게 진행되고 있다. 하지만 지속적인 high-k 물질들에 대한 연구에도 불구하고 각각의 물질이 갖는 한계점이 드러났다. 본 연구에서는 SOI기판에서 SiO2 /HfO2 (OH), SiO2/Al2O3 (OA) 이단 적층 그리고 SiO2/HfO2/Al2O3 (OHA) 삼단적층 감지막을 갖는 ISFET을 제작하고 각 감지막의 특성을 평가하였다. 평가된 특성의 결과가 아래의 표1에 요약되었다. 그 결과, 각 high-k 물질이 갖는 한계점을 극복하기 위하여 제안된 OHA감지막은 기존에 OH, OA가 갖는 장점을 취하면서 단점을 최소화 시키는 최적화된 감지막의 감지특성을 보였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 한국전기전자재료학회논문지
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• 제11권1호
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• pp.33-40
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• 1998

The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.56-56
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• 2009

In this study, we fabricated the engineered $SiO_2/Si_3N_4/SiO_2$(ONO) tunnel barrier with high-k $HfO_2$ trapping layer for application high performance flash MLC(Multi Level Cell). As a result, memory device show low operation voltage and stable memory characteristics with large memory window. Therefore, the engineered tunnel barrier with ONO stacks were useful structure would be effective method for high-integrated MLC memory applications.