• Korean Journal of Metals and Materials
• /
• v.47 no.10
• /
• pp.681-685
• /
• 2009

$CeO_2$ buffer layers have been deposited on YSZ single crystal substrates via a radio-frequency sputtering method. We focused on the texture development of $CeO_2$ with out-of-plane alignment and its effects on a superconducting YBCO layer, which was deposited by metal organic deposition. $CeO_2$ layers were grown epitaxially on single crystal YSZ substrates and subsequent YBCO layers were also grown epitaxially from $CeO_2$ layers. It was observed that the intensity of $CeO_2$(200) decreased with deposition temperature. ${\theta}-2{\theta}$ scan FWHM values of $CeO_2$(200) were inversely proportional to the peak intensities of $CeO_2$(200). The sample with the lowest $CeO_2$(200) intensity and poor out-of-plane alignment showed a strong reaction with the MOD-YBCO layer resulting in a thicker $BaCeO_3$ layer. The texture and superconducting property of the YBCO layer were affected indirectly by the formation of a $BaCeO_3$ layer at the interface between the $CeO_2$ and YBCO layers.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.10
• /
• pp.865-870
• /
• 2003

The MFIS (Metal-Ferroelectric-Insulator-Semiconductor) capacitors were fabricated using a metalorganic decomposition method. Thin layers of CeO$_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the CeO$_2$ layer. The morphology of films and the interface structures of the BLT and the CeO$_2$ layers were investigated by scanning electron microscopy. The width of the memory window in the C-V curves for the MFIS structure is 2.82 V. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• Progress in Superconductivity and Cryogenics
• /
• v.6 no.4
• /
• pp.1-4
• /
• 2004

Three group samples with difference thickness of $CeO_2$ capping layer deposited by PLD were studied. Among them, one group $CeO_2$ films were deposited on stainless steel tape coated with IBAD- YSZ and $CeO_2$ buffer layer ($CeO_2$/IBAD-YSZ/SS); other two groups of $CeO_2 YSZ Y_2O_3$multi-layer were deposited on NiW substrates for fabrication of YBCO coated conductor through RABiTS approach. The pulsed laser deposition (PLD) and DC magnetron sputtering were employed to deposit these buffer layers. On the top of buffer layer, YBCO film was deposited by PLD. The effect of thickness of $CeO_2$ film on the texture of $CeO_2$ film and critical current density ($J_c$) of YBCO film were analyzed. For the case $CeO_2$ on $CeO_2$/IBAD-YSZ/SS, there was a self-epitaxy effect with the increase of $CeO_2$ film. For $YSZ/Y_2O_3$ NiW which was deposited by PLD or DC magnetron sputtering, there is not self-epitaxy effect. However, the capping layer of $CeO_2$ film deposited by PLD improved the quality of buffer layer for $YSZ/Y_2O_3$ which was deposited by DC magnetron sputtering, therefore increased the $J_c$ of YBCO film.

• Progress in Superconductivity
• /
• v.7 no.2
• /
• pp.120-129
• /
• 2006

We comparatively studied the epitaxial growth conditions of $CeO_2$ and $Y_2O_3$ thin buffers on textured Ni tapes using rf magnetron sputtering and investigated the feasibility of getting a single mixture layer or sequential layers of $CeO_2$ and $Y_2O_3$ for more simplified buffer architecture. All the buffer layers were first deposited using the reducing gas of $Ar/4%H_2$ and subsequently the reactive gas mixture of Ar and $O_2$, The crystalline quality and biaxial alignment of the films were investigated using X-ray diffraction techniques (${\Theta}-2{\Theta},\;{\phi}\;and\;{\omega}\;scans$, pole figures). The $CeO_2$ single layer exhibited well developed (200) epitaxial growth at the condition of $10%\;O_2$ below an $450^{\circ}C$, but the epitaxial property was decreased with increasing the layer thickness. $Y_2O_3$ seldom showed optimum condition for (400) epitaxial growth. The sequential architecture of $CeO_2/Y_2O_3/CeO_2$ having good epitaxial property was achieved by sputtering at a temperature of $700^{\circ}C$ on the initial $CeO_2$ bottom layer sputtered at $400^{\circ}C$. Cracking of the sputtered buffer layers was seldom observed except the double layer structure of $CeO_2/Y_2O_3$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07a
• /
• pp.326-329
• /
• 2002

In this paper, we investigated a feasibility of cerium oxide(CeO$_2$) films as a buffer layer of MFIS(metal ferroelectric insulator semiconductor) type capacitor. CeO$_2$ layer were Prepared by two step process of a low temperature film growth and subsequent RTA (rapid thermal annealing) treatment. By app1ying an ultra thin Ce metal seed layer and N$_2$ Plasma treatment, dielectric and interface properties were improved. It means that unwanted SiO$_2$ layer generation was successfully suppressed at the interface between He buffer layer and Si substrate. The lowest lattice mismatch of CeO$_2$ film was as low as 1.76% and average surface roughness was less than 0.7 m. The Al/CeO$_2$/Si structure shows breakdown electric field of 1.2 MV/cm, dielectric constant of more than 15.1 and interface state densities as low as 1.84${\times}$10$\^$11/ cm$\^$-1/eV$\^$-1/. After N$_2$ plasma treatment, the leakage current was reduced with about 2-order.

• Progress in Superconductivity and Cryogenics
• /
• v.13 no.1
• /
• pp.1-5
• /
• 2011

[ $CeO_2$ ]has been widely used for single buffer layer of coated conductor because of superior chemical and structural compatibility with $ReBa_2Cu_3O_{7-{\delta}}$(Re=Y, Nd, Sm, Gd, Dy, Ho, etc.). But, the surface of $CeO_2$ layer showed cracks because of the large difference in thermal expansion coefficient between metal substrate and deposited $CeO_2$ layer, when thickness of $CeO_2$ layer exceeds 100 nm on the biaxially textured Ni-3%W substrate. The deposition rate has been limited to be less than 6 $\AA$/sec in order to get a good epitaxy. In this research, we deposited $CeO_2$ single buffer layers on biaxially textured Ni-3%W substrate with 2-step process such as thin nucleation layer(>10 nm) with low deposition rate(3 $\AA$/sec) and thick homo epitaxial layer(>240 nm) with high deposition rate(30 $\AA$/sec). Effect of deposition temperature on degree of texture development was tested. Thick homo epitaxial $CeO_2$ layer with good texture without crack was obtained at $600^{\circ}C$, which has ${\Delta}{\phi}$ value of $6.2^{\circ}$, ${\Delta}{\omega}$ value of $4.3^{\circ}$ and average surface roughness(Ra) of 7.2 nm within $10{\mu}m{\times}10{\mu}m$ area. This result shows the possibility of preparing advanced Ni substrate with simplified architecture of single $CeO_2$ layer for low cost coated conductor.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.05c
• /
• pp.186-189
• /
• 2003

The MFIS capacitors were fabricated using a metalorganic decomposition method. Thin layers of $ZrO_2$ and $CeO_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the $ZrO_2$ and $CeO_2$ layer. AES show no interdiffusion and the formation of amorphous $SiO_2$ layer is suppressed by using the $ZrO_2$ and $CeO_2$ film as buffer layer between the BLT film and Si substrate. The width of the memory window in the C-V curves for the $BLT/ZrO_2/Si$ and $BLT/CeO_2/Si$ structure is 2.94 V and 1.3V, respectively. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• Proceedings of the Korean Vacuum Society Conference
• /
• 1999.07a
• /
• pp.103-103
• /
• 1999

CeO2 는 cubic 구조의 일종인 CeF2 구조를 가지며 격자 상수가 0.541nm로 Si의 격자 상수 0.543nm와 거의 비슷하여 Si과의 부정합도가 0.35%에 불과하여 CeO2를 Si 기판 위에 에피택셜하게 성장시킬 수 있는 가능성이 크다. 따라서 SOI(Silicon-On-Insulator) 구조의 실현을 위하여 Si 기판위에 CeO2를 에피택셜하게 성장시키려는 많은 노력이 있었다. 또한 CeO2 는 열 적으로 대단히 안정된 물질로서 금속/강유전체/반도체 전계효과 트랜지스터(MFSFET : metal-ferroelectric-semiconductor field effect transistor)에서 ferroelectric 박막과 Si 기판사이에 완충층으로 사용되어 강유전체의 구성 원자와 Si 원자들간의 상호 확산을 방지함으로써 경계면의 특성을 향상시기키 위해 사용된다. e-beam evaporation와 laser ablation에 의한 Si 기판 위의 CeO2 격자 성장에 관한 많은 보고서가 있다. 이 방법들은 대규모 생산 공정에서 사용하기 어려운 반면 RF-magnetron sputtering은 대규모 반도체 공정에 널리 쓰인다. Sputtering에 의한 Si 기판위의 CeO2 막의 성장에 관한 보고서의 수는 매우 적다. 이 논문에서는 Ce target을 사용한 reactive rf-magnetron sputtering에 의해 Si(100) 과 Si(111) 기판위에 성장된 CeO2 의 구조 및 전기적 특성을 보고하고자 한다. 주요한 증착 변수인 증착 power와 증착온도, Seed Layer Time이 성장막의 결정성에 미치는 영향을 XRD(X-Ray Diffractometry) 분석과 TED(Transmission Electron Diffration) 분석에 의해 연구하였고 CeO2 /Si 구조의 C-V(capacitance-voltage)특성을 분석함으로써 증차된 CeO2 막과 실리콘 기판과의 계면 특성을 연구하였다. CeO2 와 Si 사이의 계면을 TEM 측정에 의해 분석하였고, Ce와 O의 화학적 조성비를 RBS에 의해 측정하였다. Si(100) 기판위에 증착된 CeO2 는 $600^{\circ}C$ 낮은 증착률에서 seed layer를 하지 않은 조건에서 CeO2 (200) 방향으로 우선 성장하였으며, Si(111) 기판 위의 CeO2 박막은 40$0^{\circ}C$ 높은 증착률에서 seed layer를 2분이상 한 조건에서 CeO2 (111) 방향으로 우선 성장하였다. TEM 분석에서 CeO2 와 Si 기판사이에서 계면에서 얇은 SiO2층이 형성되었으며, TED 분석은 Si(100) 과 Si(111) 위에 증착한 CeO2 박막이 각각 우선 방향성을 가진 다결정임을 보여주었다. C-V 곡선에서 나타난 Hysteresis는 CeO2 박막과 Si 사이의 결함때문이라고 사료된다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.05a
• /
• pp.469-472
• /
• 1999

CeO$_2$ thin films have used in wide applications such as SOI, buffer layer, antirflection coating, and gate dielectric layer. CeO$_2$takes one of the cubic system of fluorite structure and shows similar lattice constant (a=0.541nm) to silicon (a=0.543nm). We investigated CeO$_2$films as buffer layer material for nonvolatile memory device application of a single transistor. Aiming at the single transistor FRAM device with a gate region configuration of PZT/CeO$_2$ /P-Si , this paper focused on CeO$_2$-Si interface properties. CeO$_2$ films were grown on P-type Si(100) substrates by 13.56MHz RF magnetron sputtering system using a 2 inch Ce metal target. To characterize the CeO$_2$ films, we employed an XRD, AFM, C-V, and I-V for structural, surface morphological, and electrical property investigations, respectively. This paper demonstrates the best lattice mismatch as low as 0.2 % and average surface roughness down to 6.8 $\AA$. MIS structure of CeO$_2$ shows that breakdown electric field of 1.2 MV/cm, dielectric constant around 13.6 at growth temperature of 200 $^{\circ}C$, and interface state densities as low as 1.84$\times$10$^{11}$ cm $^{-1}$ eV$^{-1}$ . We probes the material properties of CeO$_2$ films for a buffer layer of FRAM applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.268-269
• /
• 2005

YBCO 박막형 초전도체(coated conductor) 제조를 위해서는 여러 층의 완충층이 필요하다. 현재 일반적인 완충층의 구조는 seed layer로써 $Y_2O_3$, diffusion barrier로 YSZ, capping layer로 $CeO_2$가 사용되고 있다. 특히, capping layer로 $CeO_2$는 YBCO와 lattice mismatch가 매우 우수한 산화물로 이용되고 있다 본 연구에서는 $CeO_2$ capping layer가 증착 방법에 따라 그 위에 증착되어지는 초전도층의 특성에 어떤 영향을 미치는지 연구하였다. $CeO_2$를 thermal evaporation과 PLD (pulsed laser deposition) 증착 방법으로 증착 한 후 그 위에 PLD 방법으로 YBCO를 증착하여 coated conductor의 성능을 평가하였다.