• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.11
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• pp.1274-1281
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• 1988

A new voltage-controlled oscillator based on a voltage-controlled integrator has been developed. It consists of a Schmitt-trigger and a voltage-controlled integrator, which is realized by an operational transconductance amplifier (OTA) and a grounded capacitor. The input control voltage changes the time constant of the integrator, and hence the oscillation frequency. The SPICE simulation shows that a prototype circuit, which oscillates at 12.21 KHz at 0 V, has the conversion sencitivity 2,437 Hz/V and the residual nonlinearity less than 0.68% in a control voltage range from -2 V to 2 V. It also shows that the circuit provides a temperature drift less than + 250 ppm/$^{\circ}$C for frequencies up to 100 KHz.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.10
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• pp.1065-1073
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• 2009

In this paper, the estimation method of C(t)-integral for combined mechanical and thermal loads is proposed for elastic-plastic-creep material via 3-dimensional FE analyses. Plasticity induced by initial loading makes relaxation rate different from those produced elastically. Moreover, the interactions between mechanical and thermal loads make the relaxation rate different from those produced under mechanical load alone. To quantify C(t)-integral for combined mechanical and thermal loads, the simplified formula are developed by modifying redistribution time in existing work done by Ainsworth et al..

• Honam Mathematical Journal
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• v.2 no.1
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• pp.1-8
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• 1980

논문(論文)[3] (본(本) 논문(論文) 제1부(第1部))에서 미분가능다양체(微分可能多樣體) M 위의 (n-1)차(次) 미분형식(微分型式) ${\beta}^{(n-1)}$이 Compact인 Carrier를 가지면 ${\int}d{\beta}^{(n-1)}=0$이며, (p-1)차(次) 미분형식(微分型式) ${\beta}^{(p-1)}$과 p차(次) 미분가능쇄(微分可能쇄鎖) $C^{(p)}=\Sigma\limits_ik_iS_i{^{(p)}}$에 대(對)하여 ${\int\limits_{c^{(p)}}}d{\beta}^{(p-1)}={\int\limits_{{\partial}{c}^{(p)}}}{\beta}^{(p-1)}$이 성립(成立) (Stokes 정리(定理)의 일반화(一般化))⋯등(等) M위의 적분(積分)에 관한 여러 가지 성질(性質)들을 구명(究明)하였다. 이 성질(性質)들을 토태(土台)로 하여 본(本) 논문(論文)에서는; 제2절(第2節)에서 미분가능다양체(微分可能多樣體) M위의 Lie 도함수(導函數)의 정의(定義)와 Lie적분(微分)에 관(關)한 여러가지 성질(性質)들을 고찰(考察)하고, 제3절(第3節)에서 div X와 Laplace 작용소(作用素) ${\Delta}f$의 정의(定義) 및 실(實) n차원(次元) 가부호미분가능(可符號微分可能) 다양체(多樣體) M 위에서의 divX와 ${\Delta}f$의 적분(積分)에 관(關)한 성질(性質), 즉(卽) $V=\sqrt{{\mid}g{\mid}}dx^1{\Lambda}{\cdots}{\Lambda}dx^n{\in}A^n(M)$에 대(對)하여 $$\int_MdivXV\limits=\int_M{\Delta}fv=0$$인 관계(關係)가 성립(成立)함을 구명(究明)한다. (정리(定理) 3.3)

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.39-47
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• 1998

A fourth-order $\Sigma$-$\Delta$ modulator is designed and implemented in 0.6 $\mu\textrm{m}$ CMOS technology. The modulator is verified by introducing nonlinear factors such as DC gain and slew rate in system model that determines the transfer function in S-domain and in time-domain. Dynamic range is more than 110 dB and the peak SM is 102.6 dB at a clock rate of 2.8224 MHz for voiceband signal. The structure of a ∑-$\Delta$ modulator is a modified fourth-order ∑-$\Delta$ modulator using direct feedback loop method, which improves performance and consumes less power. The transmission zero for noise is located in the first-second integrator loop, which reduces entire size of capacitors, reduces the active area of the chip, improves the performance, and reduces power dissipation. The system is stable because the output variation with respect to unit time is small compared with that of the third integrator. It is easy to implement because the size of the capacitor in the first integrator, and the size of the third integrator is small because we use the noise reduction technique. This paper represents a new design method by modeling that conceptually decides transfer function in S-domain and in Z-domain, determines the cutoff frequency of signal, maximizes signal power in each integrator, and decides optimal transmission-zero frequency for noise. The active area of the prototype chip is 5.25$\textrm{mm}^2$, and it dissipates 10 mW of power from a 5V supply.

• Journal of the Korean Institute of Telematics and Electronics
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• v.8 no.2
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• pp.24-33
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• 1971

A noble method of delta modulation by means of pair transistor circuit having negative resistance charcteristic is presented. An RC parallel circuit is inserted between two eiuitter tarminals of the pair transistor circuit, and their emitters are driven by a square pulsed current source. Basically this is a relaxation oscillator circuit. But when the value of capacitors and resistanc R, and the pulse height of driving source are properly chosen, the RC parallel circuit apparently functions as integrating circuit of driviving pulses. Compared with the integrated voltage of capacitor C, a signal input voltatage supplied in series with RC parallel circuit between two emitters makes on or off either of the pair transistors. as the result, one bit pulse is sent out from the coupling resistance terminal of conducted transistor. The circuit diagram used for this experiment is presented, it i% composed with simple mod ulster circuit, differential amplifier and pulse shaping amplifier, The characteristics of the components of this ciruit are discussed, and especially quantumized noise in this delta modulation system is discussed in order to improve the signal to noise ratio which has a close relation with circut constants, quantumized voltage, pulse height and width of driving current source.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3139-3141
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• 2000

전압제어 트랜스컨덕터를 설계하여 튜닝범 위가 넓은 Gm-C 대역통과 필터를 CMOS 공정으로 설계하였다 Gm-C 필터는 트랜스컨덕터와 캐패시터로 구성된 적분기를 기본으로 구현되고 있다. 따라서 트랜스 컨덕터는 출력단에 캐패시터를 연결하였을 때 이상적인적인 적분기의 특성에 가까울수록 필터의 특성이 좋아지고 PLL 구조의 튜닝이 용이해진다. 본 논문에서는 1:3이상의 범위에서 튜닝이 가능하고 PLL을 기본으로한 자동튜닝과 선형전압 튜닝을 조합하여 주파수 제어회로를 설계하였다.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.9
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• pp.949-956
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• 2009

The C(t)-integral describes amplitude of stress and strain rate field near a tip of stationary crack under transient creep condition. Thus the C(t)-integral is a key parameter for the high-temperature crack assessment. Estimation formulae for C(t)-integral of the cracked component operating under mechanical load alone have been provided for decades. However, high temperature structures usually work under combined mechanical and thermal load. And no investigation has provided quantitative estimates for the C(t)-integral under combined mechanical and thermal load. In this study, 3-dimensional finite element analyses were conducted to calculate the C(t)-integral of elastic-creep material under combined mechanical and thermal load. As a result, redistribution time for the crack under combined mechanical and thermal load is re-defined through FE analyses to quantify the C(t)-integral. Estimates of C(t)-integral using this proposed redistribution time agree well with FE analyses results.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.5
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• pp.795-802
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• 2002

For assessing significance of a defect in a component operating at high (creeping) temperatures, accurate estimation of fracture mechanics parameter, $C^{*}$-integral, is essential. Although the J estimation equation in the GE/EPRl handbook can be used to estimate the $C^{*}$-integral when the creep -deformation behavior can be characterized by the power law creep, such power law creep behavior is a very poor approximation for typical creep behaviors of most materials. Accordingly there can be a significant error in the $C^{*}$-integral. To overcome problems associated with GE/EPRl approach, the reference stress approach has been proposed, but the results can be sometimes unduly conservative. In this paper, a new method to estimate the $C^{*}$-integral for deflective components is proposed. This method improves the accuracy of the reference stress approach significantly. The proposed calculations are then validated against elastic -creep finite element (FE) analyses for four different cracked geometries following various creep -deformation constitutive laws. Comparison of the FE $C^{*}$-integral values with those calculated from the proposed method shows good agreements.greements.

• Journal of Welding and Joining
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• v.14 no.1
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• pp.38-46
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• 1996

High temperature low cycle fatigue crack growth behavior is investigated over a range of two temperatures and various frequencies in SUS 304 stainless steel. It is found that low frequency and temperature can enhance time-dependent crack growth. With high temperature, low frequency and long crack length, ${\Delta}J_c/{\Delta}J_ f$, the ratio of creep J integral range to fatigue J integral range is increased and time-dependent crack growth is accelerated. Interaction between ${\Delta}J_f$ and ${\Delta}J_c$ is occured at high frequency and low temparature and ${\Delta}J_c$, creep J integral range is fracture mechanical parameter on transition from cycle-dependent to time dependent crack growth in creep temperature region.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.1
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• pp.51-59
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• 1998

The purposes of the paper are to consider the failure phenomenon based on delamination and crack when the encapsulant of plastic IC package under hygrothermal loading in the IR soldering process is on elastic and viscoelastic behavior due to the temperature and to show the optimum design using fracture mechanics. The model for analysis is the plastic SOJ package with a dimpled diepad. The package model with the perfect delamination between chip and diepad is chosen to estimate the resistance to fracture by calculating J-integrals in low temperature and C(t)-integrals in high temperature with the change of the design under hygrothermal loading. The optimum design to depress the delamination and crack in the plastic IC package is presented.