This paper describes the design of a network interface controller (NIC) chip which is to be used to support a novel adaptive virtual cut-through routing method for parallel compute systems with direct (i.e., point-to-point) interconnection networks. The NIC chip is designed to provide the interface between a processing node constructed from commercially available microprocessors and another custom-designed router chip, which in turn performs the actual routing of packets to their respective destinations. The NIC, designed using a semi-full-custom VLSi design technique outperform traditional wormhole routing with a minimal amount of hardware overhead. The NIC design has been fully simulated and laid out using a 0.8$\mu\textrm{m}$ CMOS process.

To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. Combinational Structure has been developed to avoid the use of sequential test generator. But the patterns sifted on scan register have to be held for sequential depth period upon the aid of the dedicated HOLD circuit. In this paper, a new levelized structure is introduced aiming to exclude the need of extra HOLD circuit. The time to stimulate each scan latch is uniquely determined on this structure, hence each test pattern can e applied by scan shifting and then pulsing a system clock like the full scan but with much les scan flip-flops. Experimental results show that some sequential circuits are levelized by just scanning self-loop flip-flops.

In delay-optimized designs, timing failures due to manufacturing delay defects are more likely to occur because the average timing slacks of paths decrease and the system becomes more sensitive to smaller delay defect sizes. In this paper, the impact of delay optimized logic circuits on delay fault testing will be discussed and compared to the case for non-optimized designs. First, we provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Next we also discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults. Finally, we will give some recommendations on the determination of the system clock time so that the delay-optimized design will have the same manufacturing yield as the non-optimized design and on the determination of delay fault coverage in the delay-optimized design in order to have the same defect-level for delay faults as the non-optimized design, while the system clock time is the same for both designs.

In this paper, we propose an efficient multicast addressing scheme for he self-routing multistage networks. Using only N-bit routing header an the simple hardware logic, the new scheme can efficiently provides all point-to-multipoint connections in single pass through the multistage copy networks. We also designed a hardware logic of switching element to implementation of multicasting in ATM switches are performed.

Two asymptotic analyses of the queue length distribution at a statistical multiplexor supporting heterogeneous exponential on-off sources are considered. The first analysis is performed by approximating the cell generation rates as a multi-dimensional Ornstein-Uhlenbeck process and then applying the Benes queueing formula. In the second analysis, w state with a system of linear equations derived from the exact expressions of the dominant eigenvalue of the matrix governing the queue length distribution. Assuming that there are a large number of sources, we obtain asymptotic approximations to the dominant eigenvalue. Based on the analyses, we define a traffic descriptor to include the mean and the variance of the cell generation rate and a burstiness measure. A simple expression for the quality of service (QoS) in cell loss rate is derived in terms of the traffic descriptor parameters and the multiplexor parameters (output link capacity and buffer size). The result is then used to quantify the factors determining the required capacity of a call taking the statistical multiplexing gain into consideration. As an application of the analyses, we can use the required capacity calculation for simple yet effective connection admission control(CAC) algorithms.

In this paper, we describe the design, implementation and evaluation for a multimedia conferencing system with intramedia and intermedia synchronization support between audio and video. The synchronization mechanism proposed here is capable of dynamically adapting to various network conditions thus providing an optimized QoS. In realizing the system based on this mechanism, NeVoT on Mbone is used for audio and VIC for video. Furthermore a synchromization controller is designed and realized with a unique process in supporting intermedia synchronization. Each media agents handling its media stream are modified with intramedia synchronization function. And a communicative function between media agents and synchronization controller is added as well for intermedia synchronization function. Each media agents function reports its buffering status to the synchronization control process which in turn send out optimized buffering delay value thus supporting intermedia synchronization. The realized system is configured and tested on Ethernet and ATM network where performance measurements were performed and its effective synchronization support has been assured.

A practically applicable collision free trajectory planning technique for tow robot systems is proposed. The robot trajectories considered in this work are composed of many segments, an at the intersection points between segments robots stop to assemble, weld, ordo other jobs by the attached a end-effectors. The proposed method is based on the Planning-Coordination Decomposition where planning is to find a trajectory of each robot independently according to their tasks and coordination is to find a velocity modification profile to avoid collision with each other. To fully utilize the independently planned trajectories and to ensure no geometrical path deviation after coordination, we develop a simple technique added the minimal delay time to avoid collision just before moving along path segments. We determine the least delay time by the graphical method in the Coordination space where collisions and coordinations are easily visualized. We classify all possible cases into 3 group and derive the optimal solution for each group.

This paper proposes an intelligent controller for brushless DC motor and load with unknown nonlinear dynamics. The proposed intelligent control system consists of a plant identifier and PID controller with varying gains. The identifier is constructed using an Auto Regressive Moving Average (ARMA) model. In order to tune the parameters of the identifier and the gains of the PID controller efficiently, e also propose a modified Evolution Strategy. Experimental results show that the proposed intelligent controller for brushless DC motor has good control performance under unknown disturbance.

The steam generator level is susceptible to the nonminimum phase in dynamics due to the thermal reverse effects known as "shrink and swell" in a pressurized water reactor. A state feedback assisted control concept is presented for the change of dynamic performance to the minimum phase the concept incorporates a nonlinear digital observer as a part of the control system. The observer is deviced to estimate the state variables that provide the true indication of water inventory by compensating for shrink and swell effects. The concept is validated with implementation into the steam generator simulation model.

A lot of experiments and analyses have been done to determine the aging mechanism of mica-epoxy composite material used for large generator stator windings in order to estimate remaining life of the generator for last decades. After degrading artificially the mica-epoxy composite material, the surface analysis is performed to analyze breakdown mechanism of insulation in air and hydrogen atmosphere; i) In the case of air atmosphere, it is observed that an aging propagation from conductor to core by partial discharge effect and the formation of cracks between layers is widely carbonized surface. ii) In case of hydrogen atmosphere, the partial discharge effect is reduced by the hydrogen pressure (4kg/$\textrm{cm}^2$). Potassium ions forming a sheet of mica is replaced by hydrogen ions, which can lead to microcracks. It is confirmed that the sizes of crack by SEM analysis are 10∼20[$\mu\textrm{m}$] in length under air, and 1∼5[$\mu\textrm{m}$] in diameter, 10∼50[$\mu\textrm{m}$] in length under hydrogen atmosphere respectively. The breakdown mechanism of sttor winding insulation materials which are composed of mica-epoxy is analyzed by the component of materials with EDS, SEM techniques. We concluded that the postassium ions of mica components are replaced by H\ulcorner, H$_3$O\ulcorner at boundary area of mica-epoxy and/or mica-mica. It is proposed that through these phenomena, the conductive layers of potassium enable creation of voids and cracks due to thermal, mechanical, electrical and environmental stresses.

In his work, the influence of wire type conducting particles on the insulation reliability of GIS has been systematically investigated when the epoxy resin based dielectric coating was made on he inner side of outer electrode. For this purpose, coaxial cylinder-type electrode was adopted in 362 kV chamber and various sizes of Cu conducting particle were used under different gas pressures. In order to elucidate the coating effect on the gas insulation, different thickness of dielectric coating has been considered and then the lift-off voltage and flashover voltages have been measured. The results shown that the dielectric coating has a remarkable influence by restraining the movement of particle in GIS system, and thus GIS insulation reliability is noticeably improved.

Ion-Sensitive Field-Effect Transistors(ISFETs) with LPCVD silicon nitride as a sensitive gate were fabricated on the basis of a CMOS process. The silicon nitride was deposited directly on a poly silicon gate-electrode. Using a specially designed measuring cell, the hydrogen ions sensing properties of the ISFET in liquid could be investigated without any bonding or encapsulation. At first, th sensitivity was estimated by simualtions according to the site-binding theory and the experimental results were analysed and compared with simulated results. The measured dta were in good agreement with the simulated results. The silicon nitride based ISFET has good linearity evaluated from correlation factor ($\geq$0.9998) and a mean pH-sensitivity of 56.8mV/pH. The maximum hysteresis width between forward(pH=3\longrightarrowpH=11)- and backward(pH=11\longrightarrowpH=3) titration was 16.7mV at pH=6.54.

This paper presents the sliding mode observer-model following (SMO-MF) power system stabilizer(PSS) for unmeasurable state variables. This SMO-MF PSS is obtained by combining the sliding mode-model following (SM-MF) including closed-loop feedback(CLF) with the full-order observer(FOO). The control input of the proposed MO-MF PSS is derived by Lyapunov's second method to determine a control input that keeps the system stable for unmeasurable plant state variables. Simulation results show that the proposed SMO-MF PSS including CLF is able to reduce the low frequency oscillation and to achieve asymptotic tracking error between the reference mode state and the estimated plant state at different initial conditions.

A nonlinear optical-microwave interaction is carried out in an uniplanar CPW-to-Slotline ring resonator on the semi-insulating GaAs substrate, in which a Schottky photodetector is monolithically integrated as a coupling gap. When the capacitive reactance of the detetor is modulated, the parametric amplification effect of the mixer occurs. In this device structure, the parametric amplification gain of 20 dB without the applied bias in RF signal is obtained. This microwave optoelectronic mixer can be used in the fiber-optic communication link.

A novel driving theory on the electrohydrodynamic (EHD) pump driven by traveling electric fields without the temperature gradient is proposed. The equations of the generating pressure and the flow rate are derived. The EHD micropump is fabricated by micromachining technology and tested. The channel heights are 50$\mu\textrm{m}$, 100$\mu\textrm{m}$ and 200$\mu\textrm{m}$ are respectively an the channel width is 3 mm. The spacing and width of the electrodes are both 40$\mu\textrm{m}$. The maximum pressure is 70.3 Pa, 35.4 Pa and 17.2 pa at he frequency of 0.2Hz for each channel height (50$\mu\textrm{m}$, 100$\mu\textrm{m}$ and 200$\mu\textrm{m}$) and the maximum flow rate is 0.90x10\ulcorner ${\mu}$$\ell$/min, 1.88x10\ulcorner ${\mu}$$\ell$/min and 4.85x10\ulcorner ${\mu}$$\ell$/min at the frequency of 0.4H for each channel height.

The performance of a shared memory multiprocessor system is very sensitive to process scheduling. w can enhance the performance of a whole system as well as of an individual process by taking the multiprocessor characteristics into account in the design of the process scheduler. In this paper, we proposed a general purpose scheduler for a shared memory multiprocessor, called the Two-Level Multi-Scan (TLMS) process scheduler, that considers the processor affinity loosely and decreases the interference among multiple processors greatly. The TLMS scheduler is composed of a local scheduler at each processor and a semi-global scheduler that balances the load among processors. In particular, the semi-global scheduler tries to minimize priority inversion, which is an important factor of the system performance. The TLMS scheduler also tries to reduce the number of resources to be shared and improves the processor utilization. to meet these requirements, th semi-global scheduler interacts with the operation of the local scheduler when a need arises, thus the name is loose processor-affinity. We also show that the proposed scheduling technique can be extended for other types of resources making it a general purpose resource management queue.

An adaptive input-output linearization technique for a robust speed control of a brushless C(BLDC) motor is presented. By using this technique, the nonlinear moro model can be effectively linearized in Brunovski canonical form, an the desired speed dynamics can be obtained based on the linearized model. This control technique, however, gives an undesirable output performance under the mismatch of the system parameters and load conditions caused by the incomplete linearization. for the robust output response, the controller parameters will be estimated by a model reference adaptive technique where the disturbance torque and flux linkage are estimated. The adaptation laws are derived by the Popov's hyperstability theory nd positivity concept. The proposed control scheme is implemented on a BLDC motor using the software of DSP TMS320C30 and the effectiveness is verified through the comparative simualtions and experiments.

Design of single stage AC/DC converter with high power factor for low power level applications is proposed. The proposed converter gives the good power factor correction, low line current harmonic distortions, and tight output voltage regulations. This converter also has a high efficiency by employing an active clamp method and synchronous rectifiers. To verify the performances of the proposed converter, a 90W-converter has been designed. The modelling of this proposed converter is power formed using an averaging technique and based on this model a detailed analysis is carried out. This prototype meets the IEC555-2 requirements satisfactorily with nearly unity power factor and high efficiency.

Electrical characteristics of split-gate flash EEPROM with triple polysilicon is investigated in terms of effects of floating gate and offset gate. In order to search for t the effects of offset gate on programming characteristics, threshold voltage and drain current are studied with variation of control gate voltage. The programming process is believed to depend on vertical and horizontal electric field as well as offset gate length. The erase and program threshold voltage are found to be almost constant with variation of control gate voltage above 12V, while endurance test indicates degradation of program threshold voltage. With increase of offset gate length, program threshold voltage becomes smaller and the drain source voltage just after program under constant control gate voltage becomes higher.