This paper proposes a new real-time 2-D convolver filter architecture wihtout using any multiplier. To meet the massive amount of computations for real-time image processing, several commercial 2-D convolver chips have many multipliers occupying large VLSI area. Te proposed architecture using only one shift-and-accumulator can reduce the chip size by more than 70% of commercial 2-D convolver filter chips and can meet the real-time image processing srequirement, i.e., the standard of CCIR601. In addition, the proposed chip can be used for not only 2-D image processing but also 1-D signal processing and has bood scalability for higher speed applications. We have simulated the architecture by using VHDL models and have performed logic synthesis. We used the samsung SOG cell library (KG60K) and verified completely function and timing simulations. The implemented filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement, that is, 720*480 pixels per frame and 30 frames per second (10.4 mpixels/second).

In FPGAs, we may use the property of the routing architecture for their routing compared to the routing in the conventional layout style. Especially, the Xilinx XC4000 series FPGAs have very special routing architecture in which the routing problem is equivalent to the two dimensional track assignment problem. In this paper, we propose a new FPgA detailed routing method by developing a two dimensional trackassigment heuristic algorithm. The proposed routing mehtod accept a global routing result as an input and obtain a detailed routing such that the number of necessary wire segments in each connection block is minimized. For all benchmark circuits tested, our routing methd complete routing results. The number of used tracks are also similar to the results by thedirect routing methods.

Novel class AB CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well CMOS process for high-frequency current-mode signal processing were developed. The CCII for low power operation consists of a class AB push-pull stage for the current input, a complementary source follower for the voltage input, and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated CCII show that the current input impedance is 875.ohm. and the bandwidth of flat gain when used as a voltage amplifier extends beyond 4MHz. The power dissipation is 1.25mW and the active chip area is 0.2*0.15[mm$\^$2/].

In this paper, we propose a new scheme for the generation of partial products for VLSI fast parallel multiplier. It adopts a new encoding method which halves the number of partial products using 2x2 submultipliers and rearrangement of primitive partial products. The true 4-input CSA can be achieved with appropriate rearrangement of primitive partial products out of 2x2 submultipliers using the newly proposed theorem on binary number system. A 16bit x 16bit multiplier has been desinged using the proposed method and simulated to prove that the method has comparable speed and area compared to booth's encoding method. Much smaller and faster multiplier could be obtained with far optimization. The proposed scheme can be easily extended to multipliers with inputs of higher resolutions.

In the whole world, the research about the VLSI implementation of motion estimation algorithm is progressed to actively full (brute force) search algorithm research with the development of systolic array possible to parallel and pipeline processing. But, because of processing time's limit in a field to handle a huge data quantily such as a high definition television, many problems are happened to full search algorithm. In the paper, as a fast processing to using parallel scheme for the serial input image data, motion estimator of systolic array structure verifying that processing time is improved in contrast to the conventional full search algorithm.

In this paper, we present a method that can recognize face images by use of a sparse population code that is a learning model about a receptive fields of the simple cells in the primary visual cortex. Twenty front-view facial images form twenty persons were used for the training process, and 200 varied facial images, 20 per person, were used for test. The correct recognition rate was 100% for only the front-view test facial images, which include the images either with spectacles or of various expressions, while it was 90% in average for the total input images that include rotated faces. We analyzed the effect of nonlinear functon that determine the sparseness, and compared recognition rate using the sparese population code with that using eigenvectors (eigenfaces), which is compact code that makes contrast with the sparse population code.

In this paper, a technique ot estimate center positions of the circular parts under noisy condition is presented. The circle chords are segmented from the circle with successively varying angle and weighted to reduce the center estimation errors effected by the orientations of the circle chords. The weighting factors for variable length chords are adaptively detemined according to the error contribution of each chord in center estimation. Robust estimation of the center positions of the circular parts are possible even though the edge informations are partially contaminated by the non-uniform lighting or the background textures. Computer simulations for several images which are obtained for same object under real environment y camera, show that the proposed techniqeu yields 1.85 and 2.77 of estimated error-distribution for center position and radius in mean square error, that the proposed has more robust estimation than those of the conventional methods.

Neural networks has widely been be used for several practical applications such as speech, image processing, and pattern recognition. Thus, a approach to the voltage-controlled current source in areas of neural networks, the key features of CNN in locally connected only to its netighbors. Because the architecture of the interconnection elements between cells in very simple and space invariant, CNNs are suitable for VLSI implementation. In this paper, processing element of digital programmable CNN with variable template memory was implemented using CMOS circuit. CNN PE circuit was designe dto control gain for obtaining the optimal solutions in the CNN output. Performance of operation for 4*4 CNN circuit applied for fixed template and variable template analyzed with the result of simulation using HSPICE tool. As a result of simulations, the proposed variable template method verified to improve performance of operation in comparison with the fixed template method.

A design for a system to perform rapid recognition of three dimensional objects is presented, focusing on efficient indexing. In order to retrieve the best matched models without exploring all possible object matches, we have employed a bayesian framework. A decision-theoretic measure of the discriminatory power of a feature for a model object is defined in terms of posterior probability. Detectability of a featrue defined as a function of the feature itselt, viewpoint, sensor charcteristics, nd the feature detection algorithm(s) is also considered in the computation of discribminatory power. In order to speed up the indexing or selection of correct objects, we generate and verify the object hypotheses for rfeatures detected in a scene in the order of the discriminatory power of these features for model objects.

Based on the principles described in Part I, we have implemented a working prototype vision system using a feature structure called an LSG (local surface group) for generating object hypotheses. In order to verify an object hypothesis, we estimate the view of the hypothesized model object and render the model object for the computed view. The object hypothesis is then verified by finding additional features in the scene that match those present in the rendered image. Experimental results on synthetic and real range images show the effectiveness of the indexing scheme.

Because a map consists of many lines, a process of recognizing an object in a map is one to group lines that are consistent with the structure of the object. Therefore, it is important to establish an efficient method for finding lines which constitute objects. In this paper, a novel method for recognizing roads and districts in a land register map is proposed. In this method, lines that constitute objects are searched in a reduced search space by defining some relations between lines, and objects are recognized by using the structural information of the objects. As a result, the search space is reduced effetively, and even objects that embody the broken lines and the crossed lines are recognized.

In this work, we proesent a bidirectional approximate reasoning method and fuzzy inference network for interval valued decision making systems. For this, we propose a new type of similarity measure between two fuzzy vectors based on the Ordered Weighted Averaging (OWA) operator. Since the proposed similarity measure has a structure to give the extreme values by choosing a suitable weighting vector of the OWA operator, it can render an interval valued similarity value. From this property, we derive a bidirectional approximate reasoning method based on the similarity measure and show its fuzzy inference network implementation for the decision making systems requiring the interval valued decisions.