Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Study of W-band Low Noise Amplifier for Enhancing Noise Figure

잡음 지수 향상을 위한 W대역 저잡음 증폭기 연구

  • Kichul Kim (Space Technology Center, Advanced Defense Science & Technology Research Institute (ADSTRI), Agency for Defense Development (ADD)) ;
  • Byungjae Kim (Space Technology Center, Advanced Defense Science & Technology Research Institute (ADSTRI), Agency for Defense Development (ADD)) ;
  • Kyungyoul Park (Space Technology Center, Advanced Defense Science & Technology Research Institute (ADSTRI), Agency for Defense Development (ADD))
  • Received : 2023.03.21
  • Accepted : 2023.06.22
  • Published : 2023.06.30
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Abstract

This paper presents the optimal structure for enhancing the noise figure of a low noise amplifier(LNA) in situations where transmitted signals leak into the receiving parts. For improving performance of an LNA, a novel composite structure which incorporates the smaller transistors is newly proposed. It was confirmed that, when the transistor size being held constant, the proposed composite structure exhibited better noise figure performance compared to a general LNA structure (i.e., a single-unit transistor with a large gate width) which aims to maximized input power. We incorporated the proposed composite structure into the 1st and 2nd stages of the 4-stage LNA, while employing the general structure with a single-unit transistor for the 3rd and 4th stages. This 4-stage LNA was designed using WIN Semiconductor's 0.1-㎛ InGaAs pHEMT process (PP1011 process), and its resulting layout size is 2,100 × 1,280 ㎛2. The simulation results for the newly designed LNA, which considered its eletro-magnetic (EM) characteristics, demonstrated a gain of 17.0 dB, a noise figure of 4.0 dB, and an input 1dB gain compression point (IP1dB) of -5.7 dBm at the 80 GHz band.

본 논문은 송신 신호가 수신단으로 누설될 때 저잡음 증폭기의 잡음 지수 향상을 위한 최적 구조 연구에 관한 내용이다. 저잡음 증폭기 성능 향상을 위하여 작은 트랜지스터들로 분리하여 결합하는 복합 구조를 새롭게 제안하였다. 입력 최대 파워 향상을 위한 저잡음 증폭기 일반적인 구조(큰 게이트 폭의 단일 트랜지스터)에 비하여 동일한 게이트 폭 대비 잡음 지수 향상이 가능함을 확인하였다. 4단 저잡음 증폭기 설계에 있어서 1단 및 2단 증폭기에서는 본 논문에서 새롭게 제안하는 복합 구조를 적용하였고 3단 및 4단 증폭기는 트랜지스터 단일구조를 사용하였다. 제안한 복합 구조를 적용한 4단 저잡음 증폭기는 WIN Semiconductor사에서 제공하는 0.1-㎛ InGaAs pHEMT 공정(PP1011 process)을 활용하여 설계하였고, 2,100 × 1,280 ㎛2의 면적을 가진다. LNA의 EM 특성을 반영하여 새롭게 설계한 저잡음 증폭기는 80GHz 대역에서 17.6 dB의 이득, 4.0 dB의 잡음 지수 및 -5.7 dBm의 IP1dB 시뮬레이션 특성을 가진다.

Keywords

Acknowledgement

This work was supported by the Agency for Defense Development by the Korean Government(912773601)

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