Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Compact Verilog-A Model of Current-Voltage and Transient Behaviors of Memristors for Fast Circuit Simulation

빠른 회로 시뮬레이션을 위한 멤리스터의 전류-전압 및 과도 동작 콤팩트 Verilog-A 모델

  • Seung-Myeong Cho (Dept. of Electronics Engineering, Kookmin University) ;
  • Seokjin Oh (Dept. of Electronics Engineering, Kookmin University) ;
  • Rina Yoon (Dept. of Electronics Engineering, Kookmin University) ;
  • Kyeong-Sik Min (Dept. of Electronics Engineering, Kookmin University)
  • Received : 2023.05.22
  • Accepted : 2023.06.26
  • Published : 2023.06.30
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Abstract

This paper proposes and describes a compact model for the butterfly current-voltage characteristics and time-varying transient characteristics of memristors, which are attracting attention as a next-generation nonvolatile memory technology due to their advantages of low power, high integration, and fast switching speed. Specifically, we want to evaluate the accuracy of the model by comparing it to measurements of memristor devices and see if the simulation time is reduced by applying the model to circuit simulations. The error between the memristor measurements and the model in this paper is calculated to be less than 2%, showing that the model can predict the current-voltage characteristics of the memristor with high accuracy. It can be observed that utilizing the model in this paper to perform circuit simulation can cut simulation time by around 27% when compared to the prior model by comparing the simulation times of the memristor model and the previous model. The memristor compact model proposed in this paper is expected to contribute to reducing the total system design time by reducing simulation time, especially in the design of edge intelligence hardware.

본 논문은 저전력, 높은 집적도, 빠른 스위칭 속도 등의 이점으로 차세대 비휘발성 메모리 기술로 주목받고 있는 멤리스터의 butterfly 전류-전압 특성과 시간의 변화에 따른 transient 특성에 대한 콤팩트한 모델을 제안하고 이를 설명한다. 구체적으로 멤리스터 소자의 측정과 비교하여 모델의 정확도를 평가하여 회로 시뮬레이션에 본 모델을 적용하여 시뮬레이션 시간이 단축되는 것을 확인하려 한다. 멤리스터 측정과 본 논문의 모델의 오차는 2% 이하로 계산이 되어서 본 모델이 멤리스터의 전류-전압 특성을 높은 정확도로 예측할 수 있음을 보여준다. 이전 모델과 본 논문의 멤리스터 모델의 시뮬레이션 시간을 비교한 결과 본 논문의 모델을 이용해서 회로 시뮬레이션을 수행하면 이전의 모델에 비해 시뮬레이션 시간이 27% 정도 단축이 될 수 있음을 확인할 수 있다. 본 논문에서 제안한 멤리스터 콤팩트 모델은 특히 엣지 인텔리젼스 하드웨어의 설계 등에서 시뮬레이션 시간을 단축하여 시스템 총 설계 시간을 줄이는 데 기여할 수 있을 것으로 기대된다.

Keywords

Acknowledgement

The work was financially supported by NRF-2022R1A5A7000765, NRF-2021R1A2C1011631, NRF-2021M3F3A2A01037972, The CAD tools were supported by IC Design Education Center (IDEC), Daejeon, Korea.

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