과제정보
This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government (Ministry of Education)(No. 2021R1F1A1049023). The chip fabrication and EDA tool were supported by the IC Design Education Center(IDEC), Korea.
참고문헌
- S. I. Lim, "Analog Front-End Circuit Design for Bio-Potential Measurement," J. Institute of Electronics and Information Engineers, vol.50, no.11, pp.130-138, 2013. DOI: 10.5573/ieek.2013.50.11.130
- J. Ding, Y. Tang, L. Zhang, F. Yan, X. Gu and R. Wu, "A Novel Front-End Design for Bioelectrical Signal Wearable Acquisition," IEEE Sensors J., vol.19, no.18, pp.8009-8018, 2019. DOI: 10.1109/JSEN.2019.2917938
- H. Yoon, C. Lee, T. Kim, Y. Kwon and Y. Chae, "A 65-dB-SNDR Pipelined SAR ADC Using PVT-Robust Capacitively Degenerated Dynamic Amplifier," IEEE J. Solid-State Circuits, vol.58, no.4, pp.961-971, 2023. DOI: 10.1109/JSSC.2023.3235521
- Y. H. Hwang, Y. Song, J. E. Park and D. K. Jeong, "A Fully Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.30, no.10, pp.1381-1390, 2022. DOI: 10.1109/TVLSI.2022.3190927
- H. Zhang et al., "A 2.5-MHz BW, 75-dB SNDR Noise-Shaping SAR ADC With a 1st-Order Hybrid EF-CIFF Structure Assisted by Unity-Gain Buffer," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.30, no.12, pp.1928-1932, 2022. DOI: 10.1109/TVLSI.2022.3213365
- M. Kim, S. Hong and O. Kwon, "An Area-Efficient and Low-Power 12-b SAR/Single-Slope ADC Without Calibration Method for CMOS Image Sensors," IEEE Trans. Electron Devices, vol.63, no.9, pp.3599-3604, 2016. DOI: 10.1109/TED.2016.2587721
- C. C. Liu, M. C. Huang and Y. H. Tu, "A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC," IEEE J. Solid-State Circuits, vol.51, no.12, pp. 2941-2950, 2016. DOI: 10.1109/JSSC.2016.2591822