반도체디스플레이기술학회지 (Journal of the Semiconductor & Display Technology)

한국반도체디스플레이기술학회 (The Korean Society Of Semiconductor & Display Technology)
권호 표지

나노 MOSFETs의 게이트 누설 전류 노이즈 모델링

Noise Modeling of Gate Leakage Current in Nanoscale MOSFETs

  • 이종환 (상명대학교 시스템반도체공학과)
  • Lee, Jonghwan (Department of System Semiconductor Engineering, Sangmyung University)
  • 투고 : 2020.09.01
  • 심사 : 2020.09.11
  • 발행 : 2020.09.30
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초록

The physics-based compact gate leakage current noise models in nanoscale MOSFETs are developed in such a way that the models incorporate important physical effects and are suitable for circuit simulators, including QM (quantum-mechanical) effects. An emphasis on the trap-related parameters of noise models is laid to make the models adaptable to the variations in different process technologies and to make its parameters easily extractable from measured data. With the help of an accurate and generally applicable compact noise models, the compact noise models are successfully implemented into BSIM (Berkeley Short-channel IGFET Model) format. It is shown that the noise models have good agreement with measurements over the frequency, gate-source and drain-source bias ranges.

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참고문헌

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