한국정보통신학회논문지 (Journal of the Korea Institute of Information and Communication Engineering)

  • 제23권7호
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  • Pages.816-821
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  • 2019
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  • 2234-4772(pISSN)
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  • 2288-4165(eISSN)
한국정보통신학회 (The Korea Institute of Information and Commucation Engineering)
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분해능 향상을 위해 듀얼 에지 플립플롭을 사용하는 시간-디지털 변환기

A Time-to-Digital Converter Using Dual Edge Flip Flops for Improving Resolution

  • Choi, Jin-Ho (Division of Embedded IT Engineering, Busan University of Foreign Studies)
  • 투고 : 2019.05.03
  • 심사 : 2019.05.16
  • 발행 : 2019.07.31
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⟨ 이전 논문 다음 논문 ⟩

초록

듀얼에지 T 플립플롭을 사용하여 카운터 타입의 시간-디지털 변환기를 설계하였다. 시간-디지털 변환기는 공급 전압 1.5volts에서 $0.18{\mu}mCMOS$ 공정으로 설계하였다. 일반적인 시간-디지털 변환기에서 클록의 주기가 T일 때, 입력신호와 클록의 비동기로 인하여 클록의 주기에 해당하는 변환 에러가 발생한다. 그러나 본 논문에서 제안한 시간-디지털 변환기의 클록은 입력신호인 시작신호와 동기화되어 생성된다. 그 결과 시작신호와 클록의 비동기로 인해 발생할 수 있는 변환 에러는 발생하지 않는다. 그리고 카운터를 구성하는 플립플롭은 분해능 향상을 위해 클록의 상승에지와 하강에지에서 동작하는 듀얼에지 플립플롭으로 구성하였다.

A counter-type time-to-digital converter was designed using a dual edge T flip-flop. The time-to-digital converter was designed with a $0.18{\mu}m$ CMOS process at a supply voltage of 1.5 volts. In a typical time-to-digital converter, when the period of the clock is T, a conversion error corresponding to the period of the clock occurs due to the asynchronism between the input signal and the clock. However, the clock of the time-to-digital converter proposed in this paper is generated in synchronization with the start signal which is the input signal. As a result, conversion errors that may occur due to asynchronization of the start signal and the clock do not occur. The flip-flops constituting the counters are composed of dual-edge flip-flops operating at the positive and negative edges of the clock to improve the resolution.

키워드

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Fig. 1 Start and stop signals in time-to-digital converter

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Fig. 2 Time-to-digital converter (a) conventional countertype time-to-digital converter (b) proposed counter-type time-to-digital converter

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Fig. 4 The proposed time-to-digital converter

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Fig. 3 Input and output signals in conventional time-todigital converter

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Fig. 5 Input and output signals of the proposed time-to-digital converter (a)

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Fig. 6 Dual edge triggered T flip flop circuit

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Fig. 7 Clock, input TIN and output Q signals of the dual edge triggered T flip flop (a) clock signal (b) TIN signal (c) Q signal

HOJBC0_2019_v23n7_816_f0008.png 이미지

Fig. 8 Input and output signals of time-to-digital converter (a) start signal (b) stop sugnal (c) counter outputs when SEFF(single-edge flip flops) and DEFF(dual-edge flip flops) are used.

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