Fig. 1 The structure of the entire system
Fig. 2 The architecture of the DMA controller
Fig. 3 The simulation result of the wait_request signal
Fig. 7 Layout of the DMA controller
Fig. 8 The front of the proposed DMA controller
Fig. 9 The back of the proposed DMA controller
Fig. 4 Wait state initialization of the SDRAM
Fig. 5 Output of the image data from the DMA Control module
Fig. 6 The system architecture of the DMA controller
참고문헌
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피인용 문헌
- Intellino: Processor for Embedded Artificial Intelligence vol.9, pp.7, 2019, https://doi.org/10.3390/electronics9071169