전기전자학회논문지 (Journal of IKEEE)

  • 제23권2호
  • /
  • Pages.454-460
  • /
  • 2019
  • /
  • 1226-7244(pISSN)
  • /
  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
권호 표지
DOI QR코드

DOI QR Code

Linearization Method Using Variable Capacitance in Inter-Stage Matching Networks for CMOS Power Amplifier

  • 투고 : 2019.06.07
  • 심사 : 2019.06.13
  • 발행 : 2019.06.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

In this paper, a watt-level 2.4-GHz RFCMOS linear power amplifier (PA) with pre-distortion method using variable capacitance with respect to input power is demonstrated. The proposed structure is composed of a power detector and a MOS capacitor to improve the linearity of the PA. The pre-distortion based linearizer is embedded in the two-stage PA to compensate for the gain compression in the amplifier stages, it also improves the output P1dB by approximately 1 dB. The simulation results demonstrate a 1-dB gain compression power of 30.81 dBm at 2.4-GHz, and PAE is 29.24 % at the output P1dB point.

키워드

JGGJB@_2019_v23n2_454_f0001.png 이미지

Fig. 1. Concept of proposed PA.

JGGJB@_2019_v23n2_454_f0002.png 이미지

Fig. 2. Overall architecture.

JGGJB@_2019_v23n2_454_f0003.png 이미지

Fig. 3. Simulated fundamental and second order harmonic power versus RF input power.

JGGJB@_2019_v23n2_454_f0004.png 이미지

Fig. 4. Simulated operation of power detector.

JGGJB@_2019_v23n2_454_f0005.png 이미지

Fig. 5. Simulated power detector output DC voltage versus RF input power.

JGGJB@_2019_v23n2_454_f0006.png 이미지

Fig. 6. Full-schematic of the proposed linear PA using pre-distortion method.

JGGJB@_2019_v23n2_454_f0007.png 이미지

Fig. 7. Simulated capacitance and quality factor of variable capacitors.

JGGJB@_2019_v23n2_454_f0008.png 이미지

Fig. 8. Simulated Smith-chart of input node at PA.

JGGJB@_2019_v23n2_454_f0009.png 이미지

Fig. 9. Simulated total gate width of MOS capacitor versus output power of PA.

JGGJB@_2019_v23n2_454_f0010.png 이미지

Fig. 10. Simulated gain versus output power of PA.

JGGJB@_2019_v23n2_454_f0011.png 이미지

Fig. 11. Simulated PAE versus output power of PA.

JGGJB@_2019_v23n2_454_f0012.png 이미지

Fig. 12. Simulated DC power consumption of power detector.

JGGJB@_2019_v23n2_454_f0013.png 이미지

Fig. 13. Simulated output power versus input power.

Table 1. Summary of linear power amplifier performance.

JGGJB@_2019_v23n2_454_t0001.png 이미지

참고문헌

  1. N. Kalantari and J. F. Buckwalter, "A Nested Reactance Feedback Power Amplifier for Q Band Application," IEEE Trans. Microw. Theory Tech., vol.60, no.6, pp.1667-1675, 2012. DOI: 10.1109/TMTT.2012.2190751
  2. J. Dawson and T. H. Lee, "Automatic phase alignment for a fully integrated Cartesian feedback power amplifier system," IEEE J of Solid State Circuits, vol.38, no.12, pp.2269-2279, 2003. DOI: 10.1109/JSSC.2003.819090
  3. A. Gokceoglu, A. Ghadam, and M. Valkama, "Steady State Performance Analysis and Step Size Selection for LMS Adaptive Wideband Feedforward Power Amplifier Linearizer," IEEE Trans. Signal Processing, vol.60, no.1, pp.82-99, 2012. DOI: 10.1109/TSP.2011.2169254.
  4. J. J. Chen, C. M. Kung, and Y. S. Hwang, "Feedforward simple control techniqu e for on chip all digital three phase AC/DC power MOSFET converter with least components," IET Circ. Devices Syst., vol.3, no.4, pp.161-171, 2009. DOI: 10.1049/iet-cds.2008.0361
  5. Y. Y. Huang, W. Woo, H. Jeon, C. H. Lee, and J. S. Kenney, "Compact Wideband Linear CMOS Variable Gain Amplifier for Analog Predistortion Power Amplifiers," IEEE Trans. Microw. Theory Tech., vol.60, no.1, pp.68-76, 2012. DOI: 10.1109/TMTT.2011.2175234
  6. S. Ko and J. Lin, "A Linearized Cascode CMOS Power Amplifier," IEEE Wireless and Microwave Technology Conference, 2006. DOI: 10.1109/WAMICON.2006.351920
  7. K. Kim and Y. Kwon, "A Broadband Logarit hmic Power Detector in $0.13-{\mu}m$ CMOS," IEEE Microw. Wirel. Compon. Lett., vol.23, no.9, pp.498-500, 2013. DOI: 10.1109/LMWC.2013.2274994