참고문헌
- W. Kester, "Which ADC Architecture Is Right for Your Application?," Analog Dialogue, 2005.
- J. Choi, C. Park, and J. Choi, "A High-resolution Low-noise Capacitance to Digital Converter," Journal of IEIE, vol. 54, no. 12, pp. 81-87, 2017. https://doi.org/10.5573/ieie.2017.54.12.81
- Maxim, "Understanding SAR ADCs: Their Architecture and Comparison with Other ADCs," https://www.maximintegrated.com/en/app-notes/index.mvp/id/1080
- S. Choi, H. Ku, H. Son, B. Kim, H. Park, and J. Sim., "An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications," IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 404-417, 2018. DOI: 10.1109/JSSC.2017.2774287
- S. Wu and J. Wu, "A 81-dB Dynamic Range 16-MHz Bandwidth Delta-Sigma Modulator Using Background Calibration," IEEE Journal of Solid-State Circuits, vol. 48, no. 9, pp. 2170-2179, 2013. DOI: 10.1109/JSSC.2013.2264137
-
F. Mostert, D. Schinkel, W. Groothedde, L. Breems, R. Heeswijk, M. Koerts. E. Iersel. D. Groeneveld, G. Holland. P. Zeelen, D. Hissink, M. Pos, P. Wielage, F. Jorritsma, and M. Middelink, "5.1 A
$5{\times}80W$ 0.004% THD+N Automotive Multiphase Class-D Audio Amplifier with Integrated Low-latency${\Delta}{\Sigma}$ ADCs for Digitized Feedback after the Output Filter," in Proc. of IEEE International Solid-State Circuits Conference, pp. 86-87, 2017. DOI: 10.1109/ISSCC.2017.7870273 - C. Chen, Y. Zhang and G. Temes, "History, present state-of-art and future of incremental ADCs," in Proc. of European Solid-State Circuits Conference, pp. 83-86, 2016. DOI: 10.1109/ESSCIRC.2016.7598248
- Y. Jung and J. Roh, "The Incremental Delta-Sigma ADC for A Single-Electrode Capacitive Touch Sensor," j.inst.Korean.electr.electron.eng, vol. 17. no. 3, pp. 234-240, 2013. DOI : 10.7471/ikeee.2013.17.3.234
-
Y. Chae, K. Souri and K. Makinwa, "A
$6.3{\mu}W$ 20 bit Incremental Zoom-ADC with 6 ppm INL and$1{\mu}V$ Offset," IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3019-3027, 2013. DOI: 10.1109/JSSC.2013.2278737 - B. Gonen, F. Sebastino, R. Quan, R. Veldhoven, and K. Makinwa, "A Dynamic Zoom ADC with 109-dB DR for Audio Applications," IEEE Journal of Solid-State Circuits, vol. 52, no. 6, pp. 1542-1550, 2017. DOI: 10.1109/JSSC.2017.2669022
-
S. Karmakar, B. Gönen, F. Sebastino, R. Veldhoven, and K. Makinwa, "A
$280{\mu}W$ dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW," in Proc. of IEEE International Solid-State Circuits Conference, pp. 238-240, 2018.DOI: 10.1109/ISSCC.2018.8310272 - Texas Instruments, "Continuous-Time Sigma-Delta ADCs," http://www.ti.com/lit/an/snaa098/snaa098.pdf
- A. Hart and S. Voinigescu, "A 1 GHz Bandwidth Low-Pass Delta-Sigma ADC With 20-50 GHz Adjustable Sampling Rate," IEEE Journal of Solid-State Circuits, vol. 44, no. 5, pp. 1401-1414, 2009.DOI: 10.1109/JSSC.2009.2015852
- C. Weng, T. Wei, E. Alpman, C. Fu, and T. Lin, "A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer," IEEE Journal of Solid-State Circuits, vol. 51, no. 5, pp. 1235-1245, 2016.DOI: 10.1109/JSSC.2016.2532345
- A. Sukumaran and S. Pavan, "Design of Continuous-Time Delta-Sigma Modulators With Dual Switched-Capacitor Return-to-Zero DACs," IEEE Journal of Solid-State Circuits, vol. 51, no. 7, pp. 1619-1629, 2016.DOI: 10.1109/JSSC.2016.2542200
- B. Ginsburg and A. Chandrakasan, "500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC," IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 739-747, 2007.DOI: 10.1109/JSSC.2007.892169
- M. Kim, Y. Kim, Y. Kwak, and G. Ahn, "A 12-bit 200-kS/s SAR ADC with hybrid RC DAC," in Proc. of IEEE Asia Pacific Conference on Circuits and Systems, pp. 185-188, 2014. DOI: 10.1109/APCCAS.2014.7032752
- A. AlMarashli, J. Anders, J. Becker, and M. Ortmanns, "A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR = 107 dB at 80 kS/s," IEEE Journal of Solid-State Circuits, vol. 53, no. 5, pp. 1493-1507, 2018. DOI: 10.1109/JSSC.2017.2776299
- J. McNeill, K. Chan, M. Coln, C. David, and C. Brenneman, "All-digital background calibration of a successive approximation ADC using the 'Split ADC' architecture," IEEE Trans. Circuits Syst. I, vol. 58, no. 10, pp. 2355-2365 2011. DOI: 10.1109/TCSI.2011.2123590
- J. Shen, A. Shikata, L. Fernando, N. Guthrie, B. Chen, M. Maddox, N. Mascarenhas, R. Kapusta, and M. Coln, "A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 1149-1160, 2018.DOI: 10.1109/JSSC.2017.2784761