Journal of Power Electronics

The Korean Institute of Power Electronics (전력전자학회)
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A New Overlap Current Restraining Method for Current-source Rectifier

  • Qin, Haihong (Center for More Electric Aircraft Power System, Nanjing University of Aeronautics and Astronautics) ;
  • Liu, Qing (Center for More Electric Aircraft Power System, Nanjing University of Aeronautics and Astronautics) ;
  • Zhang, Ying (Center for More Electric Aircraft Power System, Nanjing University of Aeronautics and Astronautics) ;
  • Zhang, Xin (Center for More Electric Aircraft Power System, Nanjing University of Aeronautics and Astronautics) ;
  • Wang, Dan (Center for More Electric Aircraft Power System, Nanjing University of Aeronautics and Astronautics)
  • Received : 2017.06.26
  • Accepted : 2017.12.01
  • Published : 2018.03.20
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Abstract

To ensure a DC current path and avoid large voltage overshoot of the DC-link inductor, alternating PWM pulses in the current-source rectifier should be supplemented by overlap time, which generates an overlap current and causes input current distortion. In this study, the influence of overlap time is illustrated by comparing the AC-side current before and after overlap time is added. The overlap current distribution caused by overlap time is discussed under different modulation carriers, including triangle carrier, positive-going carrier, and negative-going carrier. The quantitative relationship between the extra harmonics of the AC-side current and overlap time is based on the Fourier analysis. Based on the commutation analysis, a new carrier modulation scheme that can restrain overlap current is proposed. A 3 kW prototype is established to verify the effectiveness of the influence of overlap time and the proposed restraining modulation scheme.

Keywords

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Fig. 1. Topology of the three-phase current-source PWM rectifier.

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Fig. 2. Current commutation from T1 to T3.

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Fig. 3. AC-side current during commutation operation from T1 toT3 with overlap time.

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Fig. 4. Theoretical modulation waveform and neutral voltagewaveform of each phase leg.

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Fig. 5. Current commutation in sector I (triangle carrier).

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Fig. 6. Equivalent waveform of overlap current in Phase A.

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Fig. 7. Current commutation in Sector I (positive-going sawtoothcarrier).

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Fig. 8. Current commutation in Sector I (negative-going sawtoothcarrier).

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Fig. 9. Distribution of positive-slope and negative-slope sawtoothcarriers during one modulation period.

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Fig. 10. Control block diagram of overlap current constrainingmethod.

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Fig. 11. Waveforms of the grid-side current and FFT analysis. (a) 0 μs overlap time. (b) 5 μs overlap time. (c) 10 μs overlap time. (d) 10μs overlap time with overlap current constraining method.

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Fig. 12. THD curves of second harmonic and fourth harmonicunder different overlap time conditions.

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Fig. 13. THD curve of grid-side current before and after adoptingthe overlap current constraining method.

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Fig. 14. 3 kW prototype of the current-source rectifier.

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Fig. 15. Experimental waveform of grid current and FFT analysiswith the overlap current constraining method. (a) td=10μs. (b)td=2μs.

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Fig. 16. THD curve of the grid current under different loadconditions.

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Fig. 17. Content of the second- and fourth-order harmonics underdifferent overlap times.

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Fig. 18. Waveforms of the grid-side current after using the overlapcurrent constraining method and FFT analysis ( td=10μs).

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Fig. 19. Relationship of the THD with load current under differentmodulation methods.

TABLE I OVERLAP CURRENT DISTRIBUTION IN [0-T1] (TRIANGLE CARRIER)

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TABLE II OVERLAP CURRENT DISTRIBUTION IN [T1-T2] (TRIANGLE CARRIER)

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TABLE III OVERLAP CURRENT DISTRIBUTION IN [T0-T1] (POSITIVE-GOING SAWTOOTH CARRIER)

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TABLE IV OVERLAP CURRENT DISTRIBUTION IN [T1-T2] (POSITIVE GOING SAWTOOTH CARRIER)

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TABLE V OVERLAP CURRENT IN [T0, T1] (NEGATIVE-SLOPE SAWTOOTH CARRIER)

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TABLE VI OVERLAP CURRENT IN [T1, T2](NEGATIVE-SLOPE SAWTOOTH CARRIER)

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TABLE VII SIMULATION PARAMETERS OF CSR

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