FPGA Implementation of Diode Clamped Multilevel Inverter for Speed Control of Induction Motor

Abstract

This work proposes FPGA implementation of Carrier Disposition PWM for closed loop seven level diode clamped multilevel inverter in speed control of induction motor. VLSI architecture for carrier Disposition have been introduced through which PWM signals are fed to the neutral point seven level diode clamped multilevel using which the speed of the induction motor is controlled. This proposed VLSI architecture makes the power circuit to work better with reduced stresses across the switches and a very low voltage and current total harmonic distortion (THD). The output voltages, currents, torque & speed characteristics for seven level neutral point diode clamped multilevel inverter for AC drive was studied. It has observed the proposed scheme introduces less distortion and harmonics. The results were validated using real time results.

Fig. 1. Three phase seven level diode clamped inverter

Fig. 2. Non shoot through mode equivalent circuit

Fig. 3. Shoot through mode equivalent circuit

Fig. 4. Phase disposition PWM

Fig. 5. Phase opposite disposition PWM

Fig. 6. Phase shifted carrier control technique

Fig. 7. Simulation of seven level diode clamped multilevelinverter

Fig. 8. Third harmonic injected reference waveform

Fig. 9. Stator current for phase disposition carrier PWM

Fig. 10. Line to line voltage for in phase disposition carrierPWM

Fig. 11. Phase voltage for phase disposition carrier PWM

Fig. 12. Various THD measured during simulation for PD PWM technique. (a) Line to line voltage THD (b) Phase voltage THD (c) Stator current THD

Fig. 13. Reference and actual speed

Fig. 14. Proposed Sequential Architecture for PDPWM

Fig. 15. FPGA architecture for Carrier frequency samplingmodule

Fig. 16. FPGA architecture for Reference carrier generationmodule

Fig. 17. Phase comparison module

Fig. 18. FPGA Carrier Pulse for PD PWM using Modelsim

Fig. 19. FPGA carrier pulse reference waveform for PDPWM using modelsim

Fig. 20. FPGA Carrier ？ Reference Generation PD PWMusing Modelsim

Fig. 21. FPGA PWM generation PD PWM using Modelsim

Fig. 22. FPGA Reference PD PWM using Modelsim

Fig. 23. Proposed hardware for Speed control of inductionmotor using PDPWM implemented on FPGA

Fig. 24. Wiring diagram for Diode Clamped seven levelInverter ？ one leg

Fig. 25. Power supply unit for Diode Clamped seven levelInverter ？ one leg

Fig. 26. Proposed hardware circuit set up

Fig. 27. PWM pulse generated from FPGA displayed in DSO

Fig. 28. Current THD measured using THD meter

Fig. 29. Voltage THD measured using THD meter

Fig. 30. Phase voltage THD measured using THD meter

Fig. 31. Phase current THD measured using THD meter

Table 1. Switch states for three phase seven level diode clamped inverter

Table 2. Comparison of different measures on various PWM techniques on seven level diode clamped multilevel inverter

Table 3. Parameters used of power circuit used for simulation

Table 4. Comparison of simulated and actual quantitative parameters of the proposed hardware circuit