A Novel Five-Level Flying-Capacitor Dual Buck Inverter

Abstract

This paper focuses on the development of a Five-Level Flying-Capacitor Dual Buck Inverter (FLFCDBI) based on the main circuit of dual buck inverters. This topology has been described as not having any shoot-through problems, no body-diode reverse recovery problems and the half-cycle work mode found in the traditional Multi-Level Flying-Capacitor Inverter (MLFCI). It has been shown that the flying-capacitor voltages of this inverter can be regulated by the redundant state selection within one pole. The voltage balance of the flying-capacitors can be achieved by charging or discharging in the positive (negative) half cycles by choosing the proper logical algorithms. This system has a simple structure but demonstrates improved performance and reliability. The validity of this inverter is conformed through computer-aided simulation and experimental investigations.

I. INTRODUCTION

Multi-Level Inverters (MLI) have been attracting more and more attention in terms of renewable energy sources (i.e., photovoltaic, wind and fuel cells) due to their high power levels, low voltage stress, low THD of the output waveform, and low EMI phenomenon and losses. MLI systems are generally classified as diode-clamped, cascaded or Flying-Capacitor Inverters (FCI) [1]-[7]. For constructing a circit with the same number of levels, the number of required components can be quite depending on the inverter type. For example, to build a n-level circuit: (i) n-1 divider capacitors and (n-1)×(n-2) clamping diodes are required for a diode-clamped inverter; (ii) (n-1)/2 independent DC sources are needed for a cascade inverter; and (iii) n-1 divider capacitors and (n-1)×(n-2)/2 flying-capacitors are needed for an FCI inverter [7]-[9]. In other words, to construct a circuit with the same number of levels, a FCI needs only half the number of clamping devices that are needed for a diode-clamped inverter, and it does not require multiplex DC sources like the cascade inverter. Accordingly, Flying-Capacitor Inverters are easier to expand to multi-level inverters. However, Flying-Capacitor Inverters have a severe shoot-through problem when they are compared to the diode-clamped and cascade inverters. This problem will be analyzed in following sections. Several methods including stringently controlling the switching vector, banning the modes that lead to direct shooting-through, setting the dead-time [10], [11], eliminating the zero-current crossing problem [12], [13], keeping the devices efficient in the dead-time period to avoid a narrow-pulse [14], modifying the commanded converter terminal voltages [15]-[17], modifying the lengths of the gate-drive pulses in the modulator (pulse-based methods) [18], and eliminating the reverse recovery of the parasitic diodes of the transistors [8]. However, the drawback of these methods is that they add complexity to the systems. In this paper, a Five-Level Flying-Capacitor Dual Buck Inverter (FLFCDBI) is presented based on the dual buck inverter. The Multi-Level Flying-Capacitor Dual Buck Inverter and the proposed Five-Level Flying-Capacitor Dual Buck Inverter will be described in Section II. Voltage balancing will be analyzed in Section III. Control strategies will be introduced in Section IV. Simulation and experiment results will be presented in Section V and Section VI, respectively. Finally, some conclusions will be given in Section VII.

 

II. MULTI-LEVEL FLYING CAPACITOR DUAL BUCK INVERTER AND FIVE-LEVEL FLYING CAPACITOR DUAL BUCK INVERTER

Fig. 1 shows a traditional n-level FCI diagram in which shooting-through can easily take place [19]-[26]. Fig. 2 summarizes a shooting-through fault diagram of four short-circuits. Summing up, shoot-through can easily take place in the four short circuits, i.e., (i) input voltage sources and transistors (Fig. 2(a)), (ii) input voltage sources and flying-capacitors (Fig. 2(b)), (iii) flying-capacitors (Fig. 2(c)), and (iv) flying-capacitors and transistors (Fig. 2(d)).

Fig. 1.Traditional n-level FCI.

Fig. 2.Shooting-through fault diagram of traditional FCI showing short circuit of: (a) voltage sources and transistors, (b) voltage sources and flying-capacitors, (c) flying-capacitors, and (d) flying-capacitors and transistors.

The shoot-through problem that occurs in the traditional FCI can be avoided by using Dual Buck Inverters (DBIs). DBIs have the distinct merits of a half cycle work mode, no shoot-through problems, and no reverse-recovery of the parasitic diode of the switches [20]-[24]. Fig. 3(a) and (b) show the topology and waveforms of the DBI, respectively.

Fig. 3.(a) topology of Dual buck half bridge inverter and (b) waveforms of dual buck half bridge inverter in half period work mode.

DBIs work in the positive or negative half cycle work modes. During the positive half cycles, Buck Circuit I works and the current of inductor L1 (iL1), which flows from transistor S1 or freewheels from diode D1, is above zero. During the negative half cycles, Buck Circuit II works and the current of inductor L2 (iL2), which flows from transistor S2 or freewheels from diode D2, is above zero. Therefore, in the half cycle work mode, there are no-loop currents, and the circuits can achieve more efficient and higher frequencies.

Two filtering inductors L1 and L2, which are in series, are connected to two switches S1 and S2, which eliminates the problem of shooting-through [21], [23]-[25], [27]-[28]. Due to this, all of the switch combinations can be used without setting the dead-time and the reliability of the system increases.

Fast Recovery Diodes (FRDs) D1 and D2 take the place of the parasitic diode of switches S1 and S2 which overcomes shortcomings such as too large a reverse recovery current, too long a reverse recovery time, and too much loss of the parasitic diode [20], [21], [23]-[25], and [28]. In addition, the efficiency can be improved, the frequency can be increased, and the volume and weight of the model can be decreased.

Furthermore voltage balancing of the flying-capacitor can be achieved by selecting proper redundant switch combinations to charge or discharge the flying-capacitors through proper logical algorithms.

Fig. 4 shows the topology of the Flying-Capacitor Dual Buck Multilevel Inverter (FCDBMLI), which is a combination of a FCI and a DBI. This topology has the benefits of both the FCI and the DBI.

Fig. 4.N-level FCDBMLI.

Table I lists the number of components of the FCDBMLI. The switch number for n-levels is n+1 (when n is odd) or n (when n is even). Table II lists the number of components for a traditional FCI [9], [19], and [23]. The switch number of a n-level traditional FCI is 2(n-1). When n>3, the switch numbers of the FCDBMLI are obviously less than those of the traditional FCI. Thus, the FCDBMLI is more cost effective than the traditional FCI, especially when the number of output levels is greater than three.

TABLE ISWITCH SCHEME AT POSITIVE HALF CYCLE

TABLE IITRADITIONAL FCI COMPONENTS

Fig. 5 shows the topology of the FLFCDBI. As mentioned earlier, the FCDBMLI is based on a DBI. Buck Circuit I consists of S11, S12, S13, D11, D12, D13, C11, C12, and L1. Buck Circuit II consists of S21, S22, S23, D21, D22, D23, C21, C22, and L2.

Fig. 5.Topology of FLFCDBI.

The modes of the FLFCDBI will be discussed together with the sequence diagram (Fig. 6), working mode diagrams (Fig. 7) and transformation diagram of the modes (Fig. 8).

Fig. 6.Sequence diagram of FLFCDBI.

Fig. 7.Working modes of FLFCDBI: (a) Mode I-0, (b)Mode I-1, (c) Mode I-2, (d) Mode I-3, (e) Mode I-4, (f) Mode I-5, (g) Mode I-6, and (h) Mode I-7.

Fig. 8.Transformation of modes.

To commence with the analysis, the following assumptions are made:

a. All of the diodes and switches are ideal;

b. All of the capacitors and inductors are ideal;

c. L1= L2=L.

When the output current iL is above zero (iL≥0, iL= iL1- iL2), the circuit works in the positive half cycle, which corresponds to the region [t0, t4] in Fig. 6. When Buck Circuit I works, Buck Curcuit II does not work. The switch combinations(Mode I-0~Mode I-7) are shown in Table III.

1) Mode I-0 (Fig. 7(a)): S11, S12 and S13 are OFF, iL1 freewheels from D11, D12 and D13, and the flying-capacitors C11 and C12 neither charge nor discharge. The voltage of pole ① is -Ud/2. In this mode:

2) Mode I-1 (Fig. 7(b)): S13 is ON, S11 and S12 are OFF, iL1 freewheels from D11 and D12, and the flying-capacitor C12 discharges. The voltage of pole ① is -Ud/4. In this mode:

3) Mode I-2 (Fig. 7(c)): S12 is ON, S11 and S13 are OFF, iL1 freewheels from D11 and D13, and the flying-capacitors C11 and C12 discharge. The voltage of pole ① is -Ud/4. In this mode:

4) Mode I-3 (Fig. 7(d)): S12 and S13 are ON, S11 is OFF, iL1 freewheels from D13, and the flying-capacitor C11 discharges. The voltage of pole ① is 0. In this mode:

5) Mode I-4 (Fig. 7(e)): S11 is ON, S12 and S13 are OFF, iL1 freewheels from D11 and D12, and the flying-capacitor C11 charges. The voltage of pole ① is 0. In this mode:

6) Mode I-5 (Fig. 7(f)): S11 and S13 are ON, S12 is OFF, iL1 freewheels from D12, the flying-capacitor C11 charges, and the flying-capacitor C12 discharges. The voltage of pole ① is Ud/4. The current iL increases. In this mode:

7) Mode I-6 (Fig. 7(g)): S11 and S12 are ON, S13 is OFF, iL1 freewheels from D11, and the flying-capacitor C12 charges. The voltage of pole ① is Ud/4. In this mode:

8) Mode I-7 (Fig. 7(h)): S11, S12 and S13 are ON, D11, D12 and D13 turn OFF, and the flying-capacitors C11 and C12 neither charge nor discharge. The voltage of pole ① is Ud/2. In this mode:

When the output current iL is less than zero, the circuit works in the negative half cycle, which corresponds to the region [t4, t8] (Fig. 6). When Buck Circuit II functions, Buck Circuit I does not function. The work modes of the negative half cycles are opposite those of the positive half cycles.

TABLE IIISWITCH SCHEME AT POSITIVE HALF CYCLE

 

III. FLYING-CAPACITOR VOLTAGE CONTROL

The voltage balancing of flying-capacitors is the key technology of this topology. It can be achieved by the charging or discharging of the flying-capacitors through choosing proper logical algorithms.

As shown in Fig. 5, x represents pole ① or ②. αxm represents the mth switch state of the pole. αxm=1, if the switch is ON; and αxm=0, if it is not. ICxn represents the current of the nth flying-capacitor of the xth pole. ILx represents the current of the xth filtering inductor. The expressions of the current of the flying-capacitor are as shown below:

The differential equations of the voltages of the flying-capacitors are as shown below:

If the equations hold during a period:

The voltage balancing of the flying-capacitors C11 and C12 can be realized.

There are redundant transferring modes corresponding to each of the four regions of the output voltage uo, [ - Uomax/2, - Uomax/4], [ - Uomax/4, 0], [0, Uomax/4], and [Uomax/4, Uomax/2]. Table 3 lists the switch combinations termed as Mode I-0 - Mode I-7, and the corresponding charging state of the flying capacitors in the positive half cycle (iL≥0). The value “1” indicates the closing state of the switches (S11, S12, and S13) and “0” indicates the closing state. The charging state of the flying-capacitors is indicated by “+”, the discharging state of the flying capacitors is indicated by “-”, and “×” indicates neither the charging nor discharging states. Fig. 8 reveals every transferring mode corresponding to each of the four regions at the positive half circle.

Since there is no transferring mode that can be implemented in the period of the four regions for achieving a voltage balance of C11 and C12 at the same time in the positive half cycle (iL≥0), two switch groups of charging (Table IV) and discharging of flying-capacitors C11 (Table V) are grouped. In each of the two groups, the voltage of C12 satisfies (16). The two groups are used to ensure that the voltage balance of these two components is done simultaneously by a hysteresis comparator with a threshold of (Δh). The logical circuit of the discharging C11 is pitched on, while vC11 (the voltage of C11) is above Ud/2+Δh (Ud is the dc-link voltage). Then vC11 begins to decrease. The logical circuit of the charging C11 is pitched on, while vC11 is below Ud/2-Δh. Then vC11 begins to increase. While vC11 is between [Ud/2-Δh , Ud/2+Δh ], the logical circuit does not switch to another circuit. This way, the voltage of C11 satisfies (15). Therefore, C11 and C12 can realize voltage balancing during a full cycle.

TABLE IVSWITCH SCHEME AT POSITIVE HALF CYCLE

TABLE VCHARGING STATES OF FLYING-CAPACITOR C11

In the negative half period (iL<0), the flying-capacitors C21 and C22 can realize the voltage balancing. These principles and methods are similar to those of the positive half cycle.

 

IV. CONTROL STRATEGY

According to the principles of the inverting and balancing of the flying-capacitor voltage of the FLFCDBI, the control block diagram is divided into four sections: the inverter circuit, region judging circuit, voltage balancing circuit, and logic circuit (Fig. 9).

Fig. 9.Control block diagram.

The inverter circuit: the control strategy adopts a two-loop system (both of the loops are PI loops): an external voltage loop and an inner current loop. The outputs of the two loops intersect on a triangular wave and generate the SPWM signals pwm1 and pwm2.

The region judging circuit: the sinusoidal signal ur is the voltage reference signal. ir is the signal of the output of the voltage loop and it is also the current reference signal. ur (ir) is compared through the zero-crossing comparator and generates Qp (ip), which indicates the positive or negative features of ur (ir). ur is compared with ±Um (Um=ur/2) and generates the signals of Q-2-1, Q0-1, Q10 and Q21, which correspond to the regions of -2Um≤ur≤-Um, -Um≤ur≤0, 0≤ur≤Um, and Um≤ur≤2Um, respectively.

The voltage balancing circuit: the flying-capacitor voltage Uc11 (Uc21) is compared with Ub±Δh（Ub = Ud/2) through the bleeder comparator and the hysteresis comparator and generates Uc1 (Uc2), which indicates the charging or discharging features of the flying-capacitor C11 (C21). Therefore, the charging or discharging mode can be chosen in the current positive half cycle or the current negative half cycle and realize the voltage balancing of the flying-capacitor occurs.

All of the signals created above are sent through a logic circuit and generate the signals of the switches S11, S12, S13, S21, S22 and S23. These switch functions, which are included in Fig. 6, are expressed at the discharging states of C11 and C21. They control the switches in the main circuit as show in Fig. 5. As illustrated in Fig. 6, the SPWM waves u1 and u2 are the outputs of poles ① and ②. They indicate the five-level output voltages and the voltage balancing of the flying-capacitor, and are synthesized into the sinusoidal wave uo after the filtering circuit.

 

V. SIMULATION RESULT

To test the schematics, SABER Simulation software was used to simulate the topology of the FLFCDBI. The conditions were as follows: the input DC voltage was ±180V, the output voltage was 110V/400Hz, the unit flying-capacitor was C=470μF, the output filter capacitor was Cf =10μF, the output filter inductor was L1= L2=100μH, and the output resistance was 50Ω. Fig. 10 illustrates the simulation waves at the no-load and full-load conditions. u1 is the voltage of pole ①, u2 is the voltage of pole ②, iL is the inductor current, and uo is the output voltage.

Fig. 10.(a) no load waveforms of simulation and (b) full load waveforms of simulation.

In the case of the steady state, the circuit works at the half cycle work mode. Fig. 10(a) reveals waveforms at the no-load condition. These waveforms show that the voltage phase is lagged behind the current phase by exactly 90°. In the positive half cycle, the output voltage uo rises, Buck Circuit I functions, and the output voltage of pole ① has five levels: ±Ud/2, ±Ud/4, and 0. Buck Circuit II does not function, iL2 is zero, and the voltage of pole ② u2 is uo. In the negative half cycle, the output voltage falls, Buck Circuit II functions, and the output voltage of pole ② has five levels: ±Ud/2, ±Ud/4, and 0. Buck Circuit I does not function, iL1 is zero, and the voltage of pole ① u1 is uo.

Fig. 10(b) reveals the waveforms at the full-load condition. The current phase of the inductor almost conforms to the voltage phase. In the positive half cycle, the output voltage is above zero, and the voltage of pole ① has three levels: Ud/2, Ud/4 and 0. In the negative half cycle, the output voltage is less than zero, and the voltage of pole ② has three levels: -Ud/2, -Ud/4 and 0. This simulation is in accordance with the principles and methods analyzed above.

 

VI. LABORATORY VALIDATION

An experimental prototype was built in the laboratory to verify the actual performance of the FLFCDBI. The parameters were as follows: the input DC voltage was ±180V, the output voltage was 110V/400Hz, the rated power was 1000W, the unit flying-capacitor was C=470μF, the output filter capacitor was Cf =10μF, and the output filter inductor was L1= L2=100μH. Power MOSFETs (IRFP460) were used for the controllable switching devices (S11, S12, S13, S21, S22, and S23). DSEI60-06A power diodes were used for D11, D12, D13, D21, D22, and D23.

In the steady state, the circuit works in the half cycle work modes. Fig. 11(a) and (b) reveal the waveforms at the no-load condition. The signal of Qp indicates the positive or negative features of uo. The signal of ip indicates the positive or negative features of iL. ch3 of Fig. 11(a) is the pole voltage u1, ch4 of Fig. 11(a) and ch3 of Fig. 11(b) are the output voltage uo, and ch4 of Fig. 11(b) is the inductor current iL. The waveforms of Qp and ip show the voltage phase lags behind the current phase by 90°. In the positive half cycle (ip=1), the output voltage rises, Buck Circuit I functions, and the output voltage of pole ① has five levels: ±Ud/2, ±Ud/4, and 0.

Fig. 11.(a), (b) no-load waveforms of experiment and (c), (d)full-load waveforms of experiment.

In the negative half period, the output voltage falls, Buck Circuit II functions, and the output voltage of pole ② has five levels: ±Ud/2, ±Ud/4, and 0. Buck Circuit I does not function, iL1 is zero, and the voltage of pole ① u1 is equal to uo.

Fig. 11(c) and (d) reveal the waveforms at the full-load condition. Qp, indicates the positive or negative features of uo. ip indicates the positive or negative features of iL. ch3 of Fig. 11(c) and ch1 of Fig. 11(d) are the pole voltage u1, and ch4 of Fig. 11(c) and ch3 of Fig. 11(d) are the output voltage uo. The waveforms of Qp and ip indicate that voltage has the same phase as the current. The four sections of u1 are even, the point of zero of u1 is correct, and balancing of the voltage is realized. The experimental waveforms are in accordance with the simulated waveforms.

In order to compare it with the FLFCDBI, a prototype of the dual buck half bridge inverter (DBHBI) had been built. It had the same input, output and rated power as the FLFCDBI.

The differences between them are the parameters of the output filter capacitor and filter inductors: Cf=22μF, L1=L2=400μH. Efficiency curves are shown in Fig. 12, and the FLFCDBI was shown to be more efficient. The total harmonic distortion (THD, using the symbol λTHD) of the output voltage uo was shown in Fig. 13. The λTHD values of the two inverters were similar. The performance of the FLFCDBI was better, and as mentioned above in the analysis, the volume of the filter was reduced.

Fig. 12.Efficiency curves.

Fig. 13.THD curves.

 

VII. CONCLUSION

In this paper, a theoretical analysis, simulations and experiments verified that the FLFCDBI maintained the merits associated with the DBI. Merits such as having no shoot-through problems, no parasitic diode reverse-recovery time, and functioning in the half cycle work modes, are achieved for the five-levels of the output voltages. In addition, the balancing of the voltage of the flying-capacitors was also achieved. Compared with the traditional multilevel inverter, the inverter is more reliable and is suitable for the aeronautics and astronautics field with its demand for high power. In addition, it promises a good application future in the field of reactive compensation, motor drives, new energy power generation, high-power supplies, active filters, etc. Furthermore, the input and the output share the same ground. Therefore, three FLFCDBI are convenient for interfacing with the same input DC source to construct a three-phase system. The three-phase FLFCDBI, and the single-phase FLFCDBI, has the merits of no shoot-through problem, non-body-diode reverse recovery problem and half-period work mode compared with the traditional three-phase half bridge flying capacitor clamped inverter.