참고문헌
- Y. C. Ju and R. A. Saleh, "Incremental techniques for the identification of statically sensitizable critical paths," in Proc. ACM/IEEE Design Automation Conf., pp. 541-546, 1991.
- L. Liu, D. Du, and H.-C. Chen, “An efficient parallel critical path algorithm,” IEEE Trans. Computer-Aided Design Integr. Circuits Syst., Vol. 13, No. 7, pp. 909-919, Jul. 1994. https://doi.org/10.1109/43.293948
- L. Xie and A. Davoodi, "Bound-based statisticallycritical path extraction under process variations," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., Vol. 30, No. 1, pp. 59-71, Jan. 2011. https://doi.org/10.1109/TCAD.2010.2072670
- K. Heloue et al., "Efficient block-based parameterized timing analysis covering all potentially critical paths," IEEE Trans. on CAD, Vol. 31, pp. 472-484, 2012. https://doi.org/10.1109/TCAD.2011.2175392
- S. H. C. Yen, D. C. Du, and S. Ghanta, "Efficient Algorithms for extracting the K most critical paths in timing analysis," 26th ACM/IEEE Design Automation Conference, pp. 649-654, June 1989.
- W. Qiu and D. M. H. Walker, "An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuit," in Proc. IEEE Int. Test Conf., pp. 592-601, Oct. 2003.
- J. Bhasker and R. Chadha, Static Timing Analysis for Nanometer Designs: A Practical Approach (1st ed.), New York, NY: Springer Science & Business Media, 2009.
- C. Visweswariah, K. Ravindran, K. Kalafala, S. Walker, and S. Narayan, "First-order incremental block-based statistical timing analysis" in Proc. Des. Autom. Conf., pp. 331-336, Jun. 2004.
- H. Chang and S. S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single PERT-like traversal," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., pp. 621-625, Nov. 2003.
- S. V. Kumar et al., "A Framework for Block-Based Timing Sensitivity Analysis," in Proc. Des. Autom. Conf, pp. 688-693, Jun.2008.
- L. M. Silveira and J. R. Phillips. "Efficient computation of the worst-delay corner," in Proc. Design Automation and Test in Europe, pp. 1617-1622, 2007.
- H. Li Z. He T. Lv and X. Li. "Test path selection for capturing delay failures under statistical timing model," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 21, No. 7, pp. 1210-1219, 2013. https://doi.org/10.1109/TVLSI.2012.2208661
- S. Onaissi and F. N. Najm, "A linear-time approach for static timing analysis covering all process corners," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., Vol. 27, No. 7, pp. 1291-1304, Jul. 2008. https://doi.org/10.1109/TCAD.2008.923635
- J. J. Nian, S. H. Tsai, and C. Y. Huang. "A unified multi-corner multi-mode static timing analysis engine," in ASP-DAC, pp. 669-674, 2010.
- Predictive Technology Model, downloaded from http://ptm.asu.edu/.
- N. R. Vempaty, V. Kumar and R. E. Korf, "Depthfirst vs best-first search," in: Proceedings AAAI-91, Anaheim, CA, 434-440, 1991
- W. Zhang, State-Space Search: Algorithms, Complexity, Extensions, and Applications, Springer, New York, NY, 1999.