• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.12
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• pp.1-8
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• 1991

Given the set of minimal paths between two vertices in a network, this paper shows that the system reliability can be obtained by using a Binary Decision Digram. It can be done by transforming a Boolean sum of products into a Binary Decision Diagram and the reliability can be directly derived from it. The resulting reliability expression is compact and requires relatively fewer arithmetic opersations in its evaluation. Several examples are given to show that the method using Binary Decision Diagram is conceptually casy, simple and efficient.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.1-12
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• 1999

A new algorithm of constructing binary decision diagram(BDD) for design verification of switch-level circuits is proposed in this paper. In the switch-level circuit, functions are characterized by serial and parallel connections of switches and the final logic values may have high-impedance and unstable states in addition to the logic values of 0 and 1. We extend the BDD to represent functions of switch-level circuits as acyclic graphs so called switch-level binary decision diagram (SLBDD). The function representation of the graph is in the worst case, exponential to the number of inputs. Thus, the ordering of decision variables plays a major role in graph sizes. Under the existence of pass-transistors and domino-logic of precharging circuitry, we also propose an input ordering algorithm for the efficiency in graph sizes. We conducted several experiments on various benchmark circuits and the results show that our algorithm is efficient enough to apply to functional simulation, power estimation, and fault-simulation of switch-level design.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.9
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• pp.759-767
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• 2000

OPKFDD(Ordered Pseudo-Kronecker Functional Decision Diagram)는 각 노드에서 다양한 decomposition을 취할 수 있는 Ordered-DD(Decision Diagram)의 한 종류이다. OBDD(Ordered Binary Decision Diagram)에서 각 노드는 Shannon decomposition 만을 이용하는 반면, OPKFDD는 각 노드마다 Shannon, positive Davio, negative Davio decomposition 중의 하나를 사용하도록 하며 많은 경우 매우 적은 수의 노드로 함수를 표현할 수 있다. 그러나 각 노드마다 각기 다른 확장 방법을 선택할 수 있는 특징 때문에 입력 노드에 대한 확장 방밥과 입력 변수 순서의 결정에 의해서 OPKFDD의 크기가 좌우되며 이에 대한 최적의 해를 구하는 것은 매우 어려운 문제로 알려져 있다. 본 논문에서는 DD 크기를 기준을 노드 수로 하여 기존의 BDD(Binary Decision Diagram) 자료구조에서 OPKFDD를 효율적으로 유도해내는 방법을 제시하고 complex term을 이용하여 이를 최소화하는 알고리즘을 제시한다. 그리고 입력변수 순서 결정을 위하여 다출력함수의 경우 함수간의 포함관계를 고려한 그룹-sifting과 각 노드의 확장 방법을 제안하고 실험 결과를 제시한다.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.363-370
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• 2002

OPKFDD (Ordered Pseudo-Kronecker Functional Decision Diagram) is one of ordered-DDs (Decision Diagrams) in which each node can take one of three decomposition types : Shannon, positive Davio and negative Davio decompositions. Whereas OBDD (Ordered Binary Decision Diagram) uses only the Shannon decomposition in each node, OPKFDD uses the three decompositions and generates representations of functions with smaller number of nodes than other DDs. However, this leads to the extreme difficulty of getting an optimal solution for the minimization of OPKFDD. Since an appropriate decomposition type has to be chosen for each node, the size of the representation is decided by the selection of the decomposition type. We propose a heuristic method to generate OPKFDD efficiently from the OBDD of the given function and the algorithm of the decision of decomposition type for a given variable ordering. Experimental results demonstrate the performance of the algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.65-78
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• 2017

Single Event Transient has a critical impact on highly integrated logic circuits which are currently common in various commercial and consumer electronic devices. Reliability against the soft and intermittent faults will become a key metric to evaluate such complex system on chip designs. Our previous work analyzing soft errors was focused on parallelizing and optimizing error propagation procedures for individual transient faults on logic and sequential cells. In this paper, we present a new propagation technique where a fault binary decision diagram (BDD) continues to merge every new fault generated from the subsequent logic gate traversal. BDD-based transient fault analysis has been known to provide the most accurate results that consider both electrical and logical properties for the given design. However, it suffers from a limitation in storing and handling BDDs that can be increased in size and operations by the exponential order. On the other hand, the proposed method requires only a visit to each logic gate traversal and unnecessary BDDs can be removed or reduced. This results in an approximately 20-200 fold speed increase while the existing parallelized procedure is only 3-4 times faster than the baseline algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1288-1293
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• 2005

This paper presents a design method for multiple-output combinational digital logic systems using time domain based on multiplexing(TDBM) and common multi-terminal extension decision diagrams(CMTEDD). The CMIEDDs represents extension valued multiple-output functions, while TDBM systems transmit several signals on a single lines. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams(CBDDs) and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams(CMTBDD) from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.

• Journal of KIISE
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• v.42 no.11
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• pp.1410-1422
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• 2015

In order to design a system, software developers use an object model such as the UML class diagram. Object-Relational Transformation Methodology (ORTM) is a methodology to transform the relationships that are expressed in the object model into relational database tables, and it is applied for the implementation of the designed system. Previous ORTM studies have suggested a number of transformation methods to represent one relationship. However, there is an implementation problem that is difficult to apply because the usage criteria for each transformation method do not exist. Therefore, this paper proposes a binary decision diagram-based modeling rule for each relationship. Hence, we define the conditions for distinguishing the transformation methods. By measuring the query execution time, we also evaluate the modeling rules that are required for the verification. After evaluation, we re-define the final modeling rules which are represented by propositional logic, and show that our proposed modeling rules are useful for the implementation of the designed system through a case study.

• Nuclear Engineering and Technology
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• v.40 no.7
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• pp.571-580
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• 2008

A Binary Decision Diagram (BDD) is a graph-based data structure that calculates an exact top event probability (TEP). It has been a very difficult task to develop an efficient BDD algorithm that can solve a large problem since it is highly memory consuming. In order to solve a large reliability problem within limited computational resources, many attempts have been made, such as static and dynamic variable ordering schemes, to minimize BDD size. Additional effort was the development of a ZBDD (Zero-suppressed BDD) algorithm to calculate an approximate TEP. The present method is the first successful application of a BDD truncation. The new method is an efficient method to maintain a small BDD size by a BDD truncation during a BDD calculation. The benchmark tests demonstrate the efficiency of the developed method. The TEP rapidly converges to an exact value according to a lowered truncation limit.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.111-119
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• 1997

This paper presented a method of extracting algorithm for Edge Multiple-Valued Decision Diagrams(EMVDD), a new data structure, from Binary Decision Diagram(BDD) which is resently used in constructing the digital logic systems based on the graph theory. And we discussed the function minimization method of the n-variables multiple-valued functions. The proposed method has the visible, schematical and regular properties.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.69-78
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• 1998

This paper presented a method of extracting algorithm for Edge Multiple-Valued Decision Diagrams(EMVDD), a new data structure, from Binary Decision Diagram(BDD) which is resently using in constructing the digital logic systems based on the graph theory. We discussed the function minimization method of the n-variables multiple-valued functions and showed that the algorithm had the regularity with module by which the same blocks were made concerning about the schematic property of the proposed algorithm. We showed the EMVDD of Full Adder by module construction and verified the proposed algorithm by examples. The proposed method has the visible, schematical and regular properties.