I. INTRODUCTION
The traditional phase-shifted full-bridge (PSFB) converter shown in Fig. 1(a) benefits from zero-voltage switching (ZVS) for all switches without the help of any auxiliary circuits [1], [2]. However, this PSFB converter suffers from a narrow ZVS range of lagging-leg switches under wide load variation, which severely affects its light load efficiency [2]. Given the resonance between transformer leakage inductance and parasitic junction capacitance of a rectifier diode, serious voltage spikes across the diode rectifier are generated [3], which increases the diode voltage rating and causes electromagnetic interference problems. Excessive circulating current in the primary side during the freewheeling interval also increases the primary side conduction and turn-off switching losses of the lagging-leg switches [4]-[6]. From the corresponding waveforms of a traditional PSFB converter shown in Fig. 1(b), duty losses exist in the traditional PSFB converter, which increase the turns ratio of the transformer and current stress in the diodes [2].
Fig. 1.(a) Traditional PSFB converter. (b) The corresponding waveforms.
Many studies have attempted to overcome the said problems in a traditional PSFB converter [2], [4]-[21]. In order to extend the ZVS range and eliminate voltage spike of diode rectifier, additional auxiliary circuits are required [2], [4]-[6], [8]-[11], [14], which increase complexity of the converter and cause additional conduction losses.
A new PSFB converter proposed in [4] always operates at a maximum duty ratio of 50% by varying the primary turns of the transformer, thus eliminating the circulating current and decreasing primary-side conduction losses. The power rating for switches decreased and the efficiency improved in the input-series-connected FB converter proposed in [17], [18]. However, this technique increases the controller complexity.
The transformer secondary side resonance technique is proposed in [22]-[29] to achieve zero current switching (ZCS) for the diode. The ZCS for the output diode is achieved with the resonant tank in the secondary side, whereas the ZVS for switches is realized through the active clamp technique [22]-[28]. However, such resonant technique results in an increased current stress of power switches. A hybrid switching mode step-down resonant-PWM converter is proposed in [29] to decrease the current stress of the power switch. It operates in PWM mode when the switch is turned on, whereas it operates in resonant mode when the switch is turned off. This condition decreases the current stress of the power switch.
This paper presents a full-bridge secondary dual-resonant (FB-SDR) DC–DC converter using the asymmetrical pulse width modulated (APWM) strategy, as shown in Fig. 2. A magnetizing inductor current is used in the proposed converter to achieve the ZVS for switches. The ZCS for the rectifier diodes is achieved because of the resonance between the leakage inductor and capacitor in the secondary side. Therefore, switching losses and diode reverse-recovery losses are eliminated. Circulating current losses that exist in traditional PSFB converters are largely eliminated because of the APWM strategy. Unlike traditional PSFB converters, the proposed converter can eliminate secondary voltage spikes and voltage oscillation across the rectifier diodes and clamp the diode voltage to the output voltage.
Fig. 2.Proposed FB-SDR converter.
The circuit configuration and operation principle of the proposed converter are presented in Section II. The analysis results are provided in Section III. The performance of the proposed converter is verified by the experimental results of a 1 kW 385 V/48 V prototype in Section IV. The conclusion is presented in Section V.
II. PROPOSED SECONDARY SIDE DUAL-RESONANT FULL BRIDGE CONVERTER
A. Circuit Configuration
Fig. 2 shows the circuit configuration of the proposed converter. The proposed converter is composed of a full bridge configuration with a blocking capacitor Cb on the primary side, a resonant network that consists of a leakage inductor Llk, capacitors Cr1 and Cr2 in the secondary side, output filter capacitor Co, and load R. When the transformer secondary voltage vS is positive, the leakage inductor Llk and resonant capacitor Cr1 constitute a resonant tank, capacitor voltage vcr1 increases, and capacitor voltage vcr2 decreases. When the transformer secondary voltage vS is negative, the leakage inductor Llk and resonant capacitor Cr2 constitute a resonant tank, capacitor voltage vcr1 decreases, and capacitor voltage vcr2 increases.
B. Operating Principle
The following assumptions are made to simplify the analysis of the proposed converter: power switches S1, S2, S3, and S4 are ideal except for their anti-paralleled diodes and output capacitances; the output capacitances of switches S1, S2, S3, and S4 are equal, i.e. Coss= Coss1= C oss2= C oss3=C oss4; capacitors Cb and Co are large enough that voltages Vcb and Vo can be considered constants in a switching cycle; the transformer is modeled as an equivalent circuit composed of a magnetizing inductor Lm, leakage inductor Llk, and an ideal transformer with a turns ratio of n:1, with Lm ˃˃ n2Llk. The converter operates in a steady state and Cr1 = Cr2 = Cr.
Fig. 3 illustrates key waveforms of the proposed converter in a switching cycle. The operation of power switches S1 and S4, as well as S2 and S3, are the same. Switches S1 and S3 are asymmetrical and complementary to the duty ratio D of power switch S1. Dead time exists between the on/off states of switches S1, S3 and S2, S4 to ensure safe operation of the power switches in the inverter leg. The proposed converter has seven operational modes in a switching cycle with their corresponding equivalent circuits in each operation mode as shown in Fig. 4.
Fig. 3.Key waveforms of the proposed converter.
Fig. 4.Operational modes of the proposed converter.
Mode 1 [t0 ~ t1]: At t = t0, as iP(t) is negative, the anti-paralleled diodes of switches S1 and S4 are conducted to provide the flowing path for iP(t). The magnetizing inductor current im(t) increases linearly from negative with the current slope of (Vin ˗ Vcb)/Lm. As vs is positive, diode D1 is turned on, and leakage inductor Llk and capacitor Cr1 are resonant. Thus, the current through the transformer secondary and voltage across the resonant capacitor Cr1 increase, whereas the voltage across resonant capacitor Cr2 decreases. im(t) can be expressed as follows:
where im(t0) is negative as shown in Fig. 3.
The following equation can be derived from the secondary side of the transformer:
From Equations (2) and (3), the following can be derived:
where ωr =1/ is the resonant angle frequency and Zr = is the characteristic impedance, Isp1 = [(Vin -Vcb)/n - vcr1(t0)]/Zr.
iP(t) and diode current iD1(t) can be expressed as follows:
Mode 2 [t1~t2]: As the anti-paralleled diodes of S1 and S4 are conducted in mode 1, the zero voltage turn-on of switches S1 and S4 are guaranteed. At t = t1, iP(t) increases to zero and switches S1 and S4 are turned on. im(t) increases linearly, diode D1 continues to conduct, and the resonant tank remains resonant. All the circuit equations in this operation mode are the same as those in operation mode 1.
Mode 3 [t2~t3]: At t = t2, switches S1 and S4 are turned off, and iP(t) charges the output capacitors of switches S1 and S4 as well as discharges the output capacitors of switches S3 and S2. The voltages across S1 to S4 can be expressed as follows:
where Ip1 represents the transformer primary-side current ip(t) at t = t2 as shown in Fig. 3. Z1 = 1/(ω1Coss) = 1/(2πfsCoss), where ω1 = 1/2, fs is the switching frequency, and Coss= Coss1 = Coss2 = Coss3 = Coss4. Note that Lkp is the primary-side leakage inductor of the transformer (i.e., Lkp = n2Llk).
From Equations (7a) and (7b), the time interval Tc1 for the ZVS commutation of S1 to S4 can be expressed as follows:
where t2-3 is the dead time of the gate signals of S1/S3 and S2/S4 .
Mode 4 [t3~t4]: After the resonance between capacitors Coss1 to Coss4 and primary side leakage inductor Lkp, the anti-paralleled diodes of S2 and S3 are forward biased. The gates of S2 and S3 are triggered during this time interval, and the ZVS for switches S2 and S3 are achieved. vp(t) is negative (i.e., vp(t) = Vp = ˗Vin ˗ Vcb). im(t) decreases linearly from positive to negative with the slope of ˗(Vin + Vcb)/Lm. The transformer secondary voltage is vs(t) = vp(t)/n = ˗(Vin + Vcb)/n.
The following equation can be derived from the secondary side of the transformer:
Solving Equations (9) and (10) obtains the following:
Currents iP(t) and iD1(t) can be expressed as follows:
Mode 5 [t4~t5]: As the anti-paralleled diodes of S2 and S3 are conducted, the zero voltage turn-on for switches S2 and S3 is guaranteed. At t = t4, iP(t) decreases to zero, switches S2 and S3 are turned on, and iD1(t) decreases to zero. Diode D2 is conducted to provide the current flowing path with leakage inductor Llk and capacitor Cr2.
The circuit equation in this mode can be expressed as follows:
Thus,
Currents iP(t) and iD2(t) can be expressed as follows:
When iD2(t) is equal to zero, diode D2 is turned off and the ZCS for diode D2 is achieved.
Mode 6 [t5 ~ t6]: The ZCS condition of diodes D2 is achieved at the beginning of this mode, which eliminates the reverse recovery loss of diode D2. The transformer secondary side in this mode is separated from the primary side, no power is transferred from the primary to the secondary side (Fig. 4f), and iP(t) decreases.
Mode 7 [t6~t7]: At t = t6, switches S2 and S3 are turned off, and iP(t) charges the output capacitors of switches S2 and S3 and discharges the output capacitors of switches S1 and S4. The voltages across S1 to S4 in this mode are written as follows:
where Ip2 is the transformer primary side current ip(t) at t = t6. Z2 = 1/(ωCoss) = 1/(2πfsCoss), ω1 = 1/2.
From Equation (19), the time interval Tc2 for the ZVS commutation of S1 to S4 can be expressed as follows:
where t6-7 represents the dead time of the gate signals for S1/S3 and S2/S4 .
When the output capacitors of power switches S1 and S4 are charged to the input voltage Vin, the anti-paralleled diodes of switches S1 and S4 are conducted and the next switching cycle begins.
III. CHARACTERISTICS ANALYSIS
A. Voltage Transfer Gain
Assume that the dead times in modes 3 and 7 are short enough that they can be neglected. The voltage across the transformer primary side in modes 1 and 2 is Vp1 (i.e., Vp1 = Vin-Vcb). The voltage across the transformer primary side in modes 4, 5, and 6 is Vp2, i.e., Vp2 = ˗Vin ˗ Vcb, where Vcb is the average voltage across the blocking capacitor Cb.
Applying volt-second balance to the magnetizing inductor Lm in steady state ensures that the average voltage across the clamp capacitor is expressed as follows:
The transformer primary side voltage can then be obtained as follows:
The average input power in a switching cycle is equal to the output power. Therefore,
As the transformer magnetizing inductor is large enough that the current ripple flowing through Lm is close to zero, the current ripple of iLm can be neglected. From Equations (4), (6), (11), (13), (16), and (18), Equation (23) can be solved to obtain the following:
where
with F = fr/fs , Q = 8ωrLlk/R.
Voltage transfer gain can then be derived as follows:
Fig. 5 shows the voltage gain of the proposed converter at F = 1. The maximum voltage gain can be achieved when D = 0.5.
Fig. 5.Voltage gain of the proposed converter (F = 1).
A. Comparison between the Proposed and Traditional PSFB Converters
The traditional PSFB converter shown in Fig. 1(a) is compared with the proposed converter shown in Fig. 2 in this section. The output inductor current is assumed to be a constant current source in the traditional PSFB converter to simplify the analysis. Figs. 1(b) and 3 show the key operating waveform of these two converters.
Fig. 1(b) reveals that when switch S1 is turned off, S3 and S4 are turned on simultaneously. Thus, a circulating current exists in the traditional PSFB converter, which results in additional conduction losses as shown in the shadow area in Fig. 1(b). Fig. 3 shows that when switch S1 is turned off, S2 and S3 are turned on simultaneously. The freewheeling of the primary magnetizing inductor current in a traditional PSFB converter is eliminated in the proposed converter. A small magnetizing inductor is required to achieve a wide ZVS range for all switches in the traditional PSFB converter, which results in a large current ripple and leads to additional conduction losses. It will also lose the ZVS for switches S2 and S4 at a light load because of insufficient energy fed by the transformer leakage inductor. However, the proposed converter uses the energy fed by magnetizing inductor Lm to achieve the ZVS for all the switches. Thus, enough energy is available for the ZVS operation over the full load range.
B. ZVS Condition
As enough energy is fed by the magnetizing inductor current and output current, the ZVS operation for switches S2 and S3 can be easily achieved over a wide load range (Fig. 4c). Fig. 4(g) shows that the ZVS for switches S1 and S4 can be achieved with energy fed by magnetizing inductor Lm. Thus, the ZVS condition for the switches in dead time tdead can be expressed as follows:
From the key waveform of the proposed converter, im(t6) can be expressed as follows:
Thus:
If Equation (30) is satisfied, all the switches in the proposed converter will turn on with the ZVS over full load conditions.
C. Design of Switches S1 to S4 and Diodes D1 to D2
Fig. 2 shows that the voltage stresses of all switches are Vin and the voltage of diodes D1 and D2 are clamped to the output voltage Vo. The average current that flows through diodes D1, D2 in a switching cycle is equal to the output current as follows:
Then,
From Equation (32), the current stress of diodes D1 and D2 can be obtained as follows:
D. Design of Resonant Tank (Llks and Cr1 , Cr2)
Fig. 6 shows the key current waveforms of the proposed converter with different resonant frequencies. As shown in Fig. 6, when Tr/2 ˃ DTs, where Tr is the resonant period and Ts is the switch period, the turn-off currents of switches S1 and S4 decrease and the zero-current turn-off for the diode rectifier can be achieved. This condition lowers the turn-off loss of switches S1 and S4 and reverse recovery loss of the diode rectifier. However, the peak current of switches S1 and S4 as well as the conduction loss increase. When Tr/2 ˃ (1 ˗ D)Ts, the ZCS for the diode rectifier cannot be achieved and the turn-off current of switches S1 and S4 also increases. This condition increases the reverse recovery loss of the diode rectifier and turn-off loss of switches S1 and S4. Therefore, having Tr/2 ˃ DTs and Tr/2 ˃ (1 ˗ D)Ts is not preferred. Consider the tradeoff between the reverse recovery loss of the diode rectifier and turn-off loss of switches S1 and S4, Tr should be designed such that DTs ˂ Tr/2 ˂ (1 ˗ D)Ts. Cr can then be obtained according to Tr = 2π.
Fig. 6.Key current waveforms of the proposed converter under different Tr.
IV. EXPERIMENTAL RESULTS
Experimental studies of the proposed converter have been performed to verify the above analysis results of the following converter parameters:
1) input voltage Vin = 385 V;
2) output voltage Vo = 48 V;
3) maximum output power Po = 1 kW;
4) switching frequency fs = 50 kHz.
With these parameters, the maximum output current is determined as Io = 20.8 A. fr is designed such that fs /[2(1 ˗ D)] ≤ fr ˂ fs /(2D). From the voltage gain given by Equation (27) and considering the dead time, the duty cycle D = 0.45 is designed. TDK EE55/21 core is used for the transformer design. The primary and secondary turns of the transformer are np = 38T and ns = 3T. According to Equation (30), the magnetizing inductance Lm = 1010 μH is designed to ensure the ZVS condition for all switches over the whole load conditions. The secondary leakage inductance of the transformer is Llk = 1.29 μH. According to the condition fs/[2(1 ˗ D)] ≤ fr ˂ fs/(2D), the resonant capacitor is designed as Cr = 4 μF and the resonant frequency is fr =1/ 2π = 51.4 kHz. The blocking capacitor Cb is added to set the average current that flows through primary magnetizing inductor to zero, thereby avoiding transformer saturation. Notably, Cb does not participate in resonance with Lm because the resonant frequency fm(fm =1/ 2π) of capacitor Cb and magnetizing inductance Lm is much lower than the switching frequency fs . fm = ()fs is generally selected. Thus, Cb = 1 μF is designed in the experimental circuit. The dead time of switches S1/S3 and S2/S4 is selected as 300 ns in the experimental circuit according to Equations (8) and (20). The ZVS operation for switches is fed by a magnetizing inductor current and output current. Thus, the ZVS operation can be easily achieved over a wide load range. The parameters of passive components and semiconductors are shown in Fig. 7 with the circuit parameters given in Table I.
Fig. 7.Laboratory prototype circuit of the proposed converter.
TABLE IPARAMETERS OF THE PROPOSED CONVERTER
A. Experimental Results
Fig. 8 shows key waveforms of the proposed converter at a nominal input voltage (i.e., 385 V) and under a full load of 20.8 A. All measured waveforms in the figure closely follow the theoretical waveforms described in Fig. 3. Figs. 8(d) and 8(e) also show that the secondary diode voltages vD1(t) and vD2(t) have no voltage overshoot and oscillation. The ZCS for diodes D1 and D2 can also be achieved. Fig. 9 shows the switch voltage and switch current of the proposed converter at full and 10% loads, respectively. Fig. 9 shows that all the switches in the proposed converter are turned on with the ZVS over full load conditions. Unlike PSFB converters, the circulating current and turn-off switching losses are decreased.
Fig. 8.Key experimental waveforms of the proposed converter at a full load of 20 A. (a) Vin and iin(t); (b) vAB(t) and primary current ip(t); (c) Vo, vCr1(t), and vcr2(t); (d) vD1(t) and iD1(t); (e) vD2(t) and iD2(t).
Fig. 9.Voltage and current waveforms of the proposed converter: (a) and (b): at full load; (c) and (d): at 10% of the full load.
B. Efficiency
Fig. 10 shows the efficiency at an input voltage of 385 V. The proposed converter has higher efficiency than a PSFB converter, especially under light load conditions. At light loads, the ZVS operation of traditional PSFB converter switches is difficult to achieve. The efficiency improvement of the proposed converter is achieved because of the ZVS operation over a whole load range as well as decreased circulating current and turn-off switching losses. Without secondary-voltage overshoot and oscillation, a low voltage-rating diode can be used, which also contributes to the efficiency improvement.
Fig. 10.Efficiency of the proposed converter.
IV. CONCLUSIONS
This paper presents an FB-SDR DC–DC converter that solves the drawbacks of PSFB converters, such as a narrow ZVS range against load variation, large circulating current, and serious secondary-voltage overshoot and oscillation. The theoretical analysis results show the advantage of the proposed converter over a traditional PSFB converter. The experiment results of a prototype converter verify the results of the theoretical analysis. However, given that the APWM strategy obtains the current stress of the switches, the proposed converter is available for applications in a narrow input voltage range and is also applicable to high-voltage applications such as high-voltage battery chargers(200 V–400 V).
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