Journal of information and communication convergence engineering

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Design Challenges and Solutions for Ultra-High-Density Monolithic 3D ICs

  • Panth, Shreepad (School of Electrical and Computer Engineering, Georgia Institute of Technology) ;
  • Samal, Sandeep (School of Electrical and Computer Engineering, Georgia Institute of Technology) ;
  • Yu, Yun Seop (Department of Electrical, Electronic, and Control Engineering, Hankyong National University) ;
  • Lim, Sung Kyu (School of Electrical and Computer Engineering, Georgia Institute of Technology)
  • Received : 2014.02.12
  • Accepted : 2014.05.16
  • Published : 2014.09.30
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Abstract

Monolithic three-dimensional integrated chips (3D ICs) are an emerging technology that offers an integration density that is some orders of magnitude higher than the conventional through-silicon-via (TSV)-based 3D ICs. This is due to a sequential integration process that enables extremely small monolithic inter-tier vias (MIVs). For a monolithic 3D memory, we first explore the static random-access memory (SRAM) design. Next, for digital logic, we explore several design styles. The first is transistor-level, which is a design style unique to monolithic 3D ICs that are enabled by the ultra-high-density of MIVs. We also explore gate-level and block-level design styles, which are available for TSV-based 3D ICs. For each of these design styles, we present techniques to obtain the graphic database system (GDS) layouts, and perform a signoff-quality performance and power analysis. We also discuss various challenges facing monolithic 3D ICs, such as achieving 50% footprint reduction over two-dimensional (2D) ICs, routing congestion, power delivery network design, and thermal issues. Finally, we present design techniques to overcome these challenges.

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References

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  1. Device Coupling Effects of Monolithic 3D Inverters vol.14, pp.1, 2016, https://doi.org/10.6109/jicce.2016.14.1.040