Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Second-order Sigma-Delta Modulator for Mobile BMIC Applications

모바일 기기용 BMIC를 위한 2차 시그마 델타 모듈레이터

  • Park, Chulkyu (Dept. of Electrical and Computer Engineering, University of Seoul) ;
  • Jang, Kichang (Dept. of Electrical and Computer Engineering, University of Seoul) ;
  • Kim, Hyojae (Dept. of Electrical and Computer Engineering, University of Seoul) ;
  • Choi, Joongho (Dept. of Electrical and Computer Engineering, University of Seoul)
  • Received : 2014.05.20
  • Accepted : 2014.06.18
  • Published : 2014.06.30
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Abstract

This paper presents design of the second-order sigma-delta modulator for converting voltage and temperature signals to digital ones in Battery Management IC (BMIC) for mobile applications. The second-order single-loop switched-capacitor sigma-delta modulator with 1-bit quantization in 0.13-um CMOS technology is proposed. The proposed modulator is designed using switched-opamp technique for saving power consumption. With an oversampling ratio of 256 and clock frequency of 256kHz, the modulator achieves a measured 83-dB dynamic range and a peak signal-to-(noise+distortion) ratio (SNDR) of 81.7dB. Power dissipation is about 0.66 mW at 3.3 V power supply and the occupied core area is $0.425mm^2$.

본 논문에서는 모바일 기기의 배터리 전력관리 IC(Battery Management IC)에서 전압 및 온도를 측정하여 디지털 신호로 바꾸어 주는데 필요한 시그마-델타 모듈레이터를 설계하였다. 제안하는 이산-시간 시그마-델타 모듈레이터는 2차의 단일 비트 구조이고 0.13um CMOS 공정으로 제작되었다. 모듈레이터의 소모전류를 줄이기 위하여 switched-opamp 방식을 적용하여 설계하였다. 제안하는 모듈레이터는 오버 샘플링 비율이 256 일 때 256kHz의 클락 주파수에서 83-dB의 dynamic range와 81.7dB의 peak signal-to-(noise + distortion) ratio(SNDR)를 가진다. 3.3 V의 전원전압에서 0.66 mW의 전력을 소모하며 모듈레이터 코어의 면적은 $0.425mm^2$ 이다.

Keywords

References

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