JSTS:Journal of Semiconductor Technology and Science

  • 제14권3호
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  • Pages.345-355
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  • 2014
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Efficient Parallel Scan Test Technique for Cores on AMBA-based SoC

  • Song, Jaehoon (Dept. of Computer Science & Engineering, Hanyang University ERICA Campus) ;
  • Jung, Jihun (Dept. of Computer Science & Engineering, Hanyang University ERICA Campus) ;
  • Kim, Dooyoung (Dept. of Computer Science & Engineering, Hanyang University ERICA Campus) ;
  • Park, Sungju (Dept. of Computer Science & Engineering, Hanyang University ERICA Campus)
  • 투고 : 2014.02.13
  • 심사 : 2014.04.17
  • 발행 : 2014.06.30
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초록

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

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참고문헌

  1. S. Narayanan, R. Gupta, and M. A. Breuer, "Optimal configuring of multiple scan chains," Computers, IEEE Transactions on, vol. 42, pp. 1121-1131, 1993. https://doi.org/10.1109/12.241600
  2. Z. Shanrui, C. Minsu, N. Park, and F. Lombardi, "Cost-driven optimization of fault coverage in combined Built-In Self-Test/Automated Test Equipment testing," in Instrumentation and Measurement Technology Conference, 2004. IMTC 04. Proceedings of the 21st IEEE, 2004, pp. 2021-2026 Vol.3.
  3. S. K. Goel and E. J. Marinissen, "Effective and efficient test architecture design for SOCs," in Test Conference, 2002. Proceedings. International, 2002, pp. 529-538.
  4. Y. Zorian, E. J. Marinissen, and S. Dey, "Testing embedded-core based system chips," in Test Conference, 1998. Proceedings., International, 1998, pp. 130-143.
  5. "IEEE std 1500 Standard for Embedded Core Test," http://grouper.ieee.org/groups/1500/.
  6. J. Aerts and E. J. Marinissen, "Scan chain design for test time reduction in core-based ICs," in Test Conference, 1998. Proceedings., International, 1998, pp. 448-457.
  7. P. Varma and S. Bhatia, "A structured test re-use methodology for core-based system chips," in Test Conference, 1998. Proceedings., International, 1998, pp. 294-302.
  8. S. Jaehoon, M. Piljae, Y. Hyunbean, and P. Sungju, "Design of Test Access Mechanism for AMBABased System-on-a-Chip," in VLSI Test Symposium, 2007. 25th IEEE, 2007, pp. 375-380.
  9. L. Chih-Yi and L. Hsing-Chung, "Bus-oriented DFT design for embedded cores," in Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on, 2004, pp. 561-563 vol.1.
  10. C. Feige, J. T. Pierick, C. Wouters, R. Tangelder, and H. G. Kerkhoff, "Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach," J. Electron. Test., vol. 14, pp. 125-131, 1999. https://doi.org/10.1023/A:1008313726031
  11. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. New York: Computer Science Press, 1991.
  12. E. J. Marinissen, S. K. Goel, and M. Lousberg, "Wrapper design for embedded core test," in Test Conference, 2000. Proceedings. International, 2000, pp. 911-920.
  13. K.-w. Eom, D.-k. Han, Y. Lee, H.-s. Kim, and S. Kang, "Efficient Multi-site Testing Using ATE Channel Sharing" Journal of Semiconductor Technology and Science, vol. 13, pp. 259-262, 2013. https://doi.org/10.5573/JSTS.2013.13.3.259
  14. D. K. Bhavsar and S. J. Poehlman, "Test access and the testability features of the Poulson multi-core Intel Itanium(R) processor," in Test Conference (ITC), 2011 IEEE International, 2011, pp. 1-8.
  15. X. Dong, Z. Yang, K. Chakrabarty, and H. Fujiwara, "A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, pp. 999-1012, 2008. https://doi.org/10.1109/TCAD.2008.923260
  16. Z. Jin-yi, H. Xu-hui, C. Wan-lin, and W. Han-yi, "Improved delay fault coverage in SoC using controllable multi-Scan-Enable," in Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on, 2010, pp. 1973-1975.
  17. ARM, "AMBA specification (rev. 2.0)," 1999 May.
  18. "IEEE Standard Test Access Port and Boundary- Scan Architecture," IEEE std 1149.1.
  19. E. J. Marinissen, V. Iyerngar, and K. Charkrabarty. (2002). ITC'02 SOC Test Benchmarks. Available: http://itc02socbenchm.pratt.duke.edu/