DOI QR코드

DOI QR Code

Analysis of SOHOS Flash Memory with 3-level Charge Pumping Method

  • 투고 : 2013.08.25
  • 심사 : 2013.12.18
  • 발행 : 2014.02.28

초록

This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

키워드

참고문헌

  1. M. L. French, C. Y. Chen, H. Sathianathan, and M. H. White, "Design and scaling of a SONOS multidielectric device for nonvolatile memory applications," IEEE Trans. Compon., Packag., Manuf. Technol. A, vol. 17, no. 3, pp. 390-397, Sep. 1994. https://doi.org/10.1109/95.311748
  2. J. K. Bu and M. H. White, "Design considerations in scaled SONOS nonvolatile memory devices," Solid-State Electron., vol. 45, no. 1, pp. 113- 120, Jan. 2001. https://doi.org/10.1016/S0038-1101(00)00232-X
  3. H. Wann and C. Hu, "High endurance ultrathin tunnel oxide in MONOS device structure for dynamic memory applications," IEEE Electron Device Lett., vol. 16, pp. 491-493, May 1995. https://doi.org/10.1109/55.468277
  4. Y. Kamagaki, S. I. Minami, T. Hagiwara, K. Furusawa, T. Furuno, K. Uchida, M. Terasawa, and K. Yamazaki, "Yield and reliability of MNOS EEPROM products," IEEE J. Solid-State Circuits, vol. 24, pp. 1714-1722, Nov. 1989. https://doi.org/10.1109/4.45010
  5. T. Ishida, Y. Okuyama, and R. Yamada, "Characterization of charge traps in metal-oxidenitride- oxide-semiconduct (MONOS) structure for embedded flash memories." IEEE Annu. Int. Rel. Phys. Symp., pp.516-522 (2006).
  6. Wang, Ying Qian, et al. "Electrical characteristics of memory devices with a high-k HfO2 trapping layer and dual SiO2/Si3N4 tunneling layer." IEEE transactions on electron devices 54.10 (2007): 2699-2705.
  7. T. S. Chen, K. H. Wu, H. Chung, and C. H. Kao, "Performance improvement of SONOS memory by band gap engineering of charge-trapping layer," IEEE Electron Device Lett., vol. 25, no. 4, pp. 205- 207, Apr. 2004. https://doi.org/10.1109/LED.2004.825163
  8. Wilk, Glen D., Robert M. Wallace, and J. M. Anthony. "High-$\kappa$ gate dielectrics: Current status and materials properties considerations." Journal of applied physics 89.10 (2001): 5243-5275.
  9. G. Groeseneken, H. E. Maes, N. Beltran, and R. F. Dekeersmaecker, "A reliable approach to chargepumping measurements in MOS transistors," IEEE Tmns. Electron Devices, vol. ED-31, p. 42, Jan. (1984).
  10. W. L. Tseng, "A new charge pumping method of measuring Si-Si02 interface states," J. Appl. Phys., vol. 62, p. 591, July (1987). https://doi.org/10.1063/1.339786