전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제51권2호
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  • Pages.46-52
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  • 2014
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  • 2287-5026(pISSN)
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  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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빠른 Lock-Time을 위한 다중 이득 제어 디지털 위상 주파수 검출기

A Multiple Gain Controlled Digital Phase and Frequency Detector for Fast Lock-Time

  • 홍종필 (충북대학교 전자정보대학 전기공학부)
  • Hong, Jong-Phil (Department of Electrical Engineering, Chungbuk National University)
  • 투고 : 2013.11.09
  • 발행 : 2014.02.25
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초록

본 논문은 다중 이득 제어를 통하여 빠른 lock-time을 갖는 디지털 위상 주파수 검출기 회로를 제안한다. 기준신호와 피드백 신호의 위상 차이가 클 때, 위상 차이가 적으면서 lock에 근접했을 때, lock 이후의 세 경우에 따라 디지털 위상 동기 루프의 이득을 다르게 설정하여 lock-time을 효과적으로 줄일 수 있다. 시뮬레이션 결과를 통해 제안된 기법을 적용함으로써 기존의 단일 이득 제어 구조보다 lock-time을 약 100배 개선시킬 수 있음을 확인하였다.

This paper presents a multiple gain controlled digital phase and frequency detector with a fast lock-time. Lock-time of the digital PLL can be significantly reduced by applying proposed adaptive gain control technique. A loop gain of the proposed digital PLL is controlled by three conditions that are very large phase difference between reference and feedback signal, small phase difference and before lock-state, and after lock-state. The simulation result shows that lock-time of the proposed multiple gain controlled digital PLL is 100 times faster than that of the conventional structure with unit gain mode.

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참고문헌

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