한국산업정보학회논문지 (Journal of Korea Society of Industrial Information Systems)

한국산업정보학회 (Korea Society of Industrial Information Systems)
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저전력 바이패싱 Booth 곱셈기 설계

A Design of Low-Power Bypassing Booth Multiplier

  • 안종훈 (충남대학교 컴퓨터공학과) ;
  • 최성림 (충남대학교 컴퓨터공학과) ;
  • 남병규 (충남대학교 컴퓨터공학과)
  • 투고 : 2013.09.16
  • 심사 : 2013.10.15
  • 발행 : 2013.10.31
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초록

본 논문에서는 모바일 멀티미디어 응용을 위한 저전력 바이패싱 (bypassing) Booth 곱셈기를 제안한다. 바이패싱 구조는 특정 입력 패턴에 대하여 내부 회로를 우회하여 입력 값을 출력 값으로 직접 전달하므로 내부 회로의 스위칭 전류를 방지하여 저전력 회로를 구현한다. 제안된 곱셈기는 Braun 곱셈기법에 기반을 둔 전통적인 바이패싱 곱셈기와 달리, 현재 널리 사용되는 Booth 곱셈기법에 대하여 바이패싱 구조를 적용하였다. 시뮬레이션 결과, 기존 저전력 Booth 곱셈기에 비하여 제안된 FoM (Figure-of-merit)이 11% 감소함을 확인하였다.

A low-power bypassing Booth multiplier for mobile multimedia applications is proposed. The bypassing structure directly transfers input values to outputs without switching the internal nodes of a multiplier, enabling low-power design. The proposed Booth multiplier adopts the bypassing structure while the bypassing is usually adopted in the Braun multipliers. Simulation results show the proposed Booth multiplier achieves an 11% reduction in terms of the proposed FoM compared to prior works.

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참고문헌

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