JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Channel Model of Scaled RC-dominant Wires for High-Speed Wireline Transceiver Design

  • Choi, Minsoo (Department of Electrical Engineering, Pohang University of Science and Technology) ;
  • Sim, Jae-Yoon (Department of Electrical Engineering, Pohang University of Science and Technology) ;
  • Park, Hong-June (Division of IT Convergence Engineering, Pohang University of Science and Technology) ;
  • Kim, Byungsub (Department of Creative IT Engineering, Pohang University of Science and Technology)
  • Received : 2013.05.26
  • Accepted : 2013.07.12
  • Published : 2013.10.31
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Abstract

This paper explains modeling and analysis of RC-dominant wires for high-speed wireline transceiver design. A closed form formula derived from telegrapher's equation accurately describes a frequency response of an RC-dominant wire, yet it is simple and intuitive for designers to easily understand design trade-offs without a complex numerical equation solver. This paper explains how the model is derived and how it can help designers in example transceiver designs.

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