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http://dx.doi.org/10.5573/JSTS.2013.13.5.482

A Channel Model of Scaled RC-dominant Wires for High-Speed Wireline Transceiver Design  

Choi, Minsoo (Department of Electrical Engineering, Pohang University of Science and Technology)
Sim, Jae-Yoon (Department of Electrical Engineering, Pohang University of Science and Technology)
Park, Hong-June (Division of IT Convergence Engineering, Pohang University of Science and Technology)
Kim, Byungsub (Department of Creative IT Engineering, Pohang University of Science and Technology)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.13, no.5, 2013 , pp. 482-491 More about this Journal
Abstract
This paper explains modeling and analysis of RC-dominant wires for high-speed wireline transceiver design. A closed form formula derived from telegrapher's equation accurately describes a frequency response of an RC-dominant wire, yet it is simple and intuitive for designers to easily understand design trade-offs without a complex numerical equation solver. This paper explains how the model is derived and how it can help designers in example transceiver designs.
Keywords
Channel model; RC-dominant wires; wireline transceiver design; signaling modes;
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Times Cited By KSCI : 1  (Citation Analysis)
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