참고문헌
- Muller P, Leblebici Y. CMOS multichannel singlechip receivers for multi-gigabit optical data communications [M]. New York: Springer, 2007
- Rabaey J M, Chandrakasan A, Nikolic B. Digital integrated circuits: a design perspective (second edition) [M]. London: Prentice Hall, 2003
- Tao H, Shaeffer D K, Xu M, et al. 40-43-Gb/s OC- 768 16:1 MUX/CMU chipset with SFI-5 compliance [J]. IEEE Journal of Solid-State Circuits, 2003, 38(12): 2169-2180 https://doi.org/10.1109/JSSC.2003.818575
- Kushiyama N, Ohshima S, Stark D, et al. A 500- Megabyte/s data-rate 4.5M DRAM [J]. IEEE Journal of Solid-State Circuits, 1993, 28(4): 490-498 https://doi.org/10.1109/4.210033
- Lau B, Chan Y F, Moncayo A, et al. A 2.6-GByte/s multipurpose chip-to-chip interface [J]. IEEE Journal of Solid-State Circuits, 1998, 33 (11): 1617-1626 https://doi.org/10.1109/4.726545
- Toshiro T, Takashi M, Yuji S, et al. 110-GB/s Simultaneous Bidirectional Transceiver Logic Synchronized with a System Clock [J]. IEEE Journal of Solid-State Circuits, 1999, 34(11): 1526- 1533 https://doi.org/10.1109/4.799856
- Kim K, Choi J, Choi J. Design of 250Mb/s 10- channel CMOS optical receiver array for computer communication [C]. The first IEEE Asia Pacific Conference on ASICs, AP-ASIC'99, 1999: 29-32
- Tang W, Plant D V. A 2.5-Gbps De-Skew Chip for Very Short Reach (VSR) Interconnects [C]. IEEE, LEOS, 2006: 823-824
- Yeung E. Design of High-Performance and Low- Cost Parallel Links [D]: [A dissertation for Ph.D]. Stanford University, 2002
- Chang K, Pamarti S, Kaviant K, et al. Clocking and circuit design for a parallel I/O on a first-generation CELL Processor [C]. IEEE ISSCC, 2005: 526-615
- Sato T, Nishio Y, Sugano T, et al. A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM [J]. IEEE Journal of Solid- State Circuits, 1999, 34(5): 653-660 https://doi.org/10.1109/4.760375
- Yang K, Lin T, Ke Y. A scalable 32Gb/s parallel data transceiver with on-chip timing calibration circuits [C]. IEEE ISSCC Dig. Tech. Papers, 2000 (2): 258-259
- Casper B, Jaussi J, Mahony F, et al. A 20Gb/s forwarded clock transceiver in 90nm CMOS [C]. ISSCC Dig, Tech. Papers, 2006: 90-1
- Casper B, Martin A, Jaussi J E, et al. An 8-Gb/s simultaneous bidirectional link with on-die waveform capture [J]. IEEE Journal of Solid-State Circuits, 2003, 38(12): 2111-2120 https://doi.org/10.1109/JSSC.2003.818569
- Tanahashi T, Kurisu K, Yamaguchi H, et al. A 2Gb/s 21CH low-latency transceiver circuit for inter-processor communication [C]. IEEE ISSCC Dig. Tech., Papers, 2001, (2): 60-61
- Kohtaroh G, Hideki T, Hirotaka T. A 2-byte parallel 1.25 Gb/s interconnect I/O interface with self-configurable link and plesiochronous clocking [J]. FUJITSU Sci. Tech., 2000, 36(1): 82-90
- Hossain M, Chan A. CMOS Oscillators for clock distribution and Injection-Locked Deskew [J]. IEEE Journal of Solid-State Circuits, 2009, 44(8): 2138-2153 https://doi.org/10.1109/JSSC.2009.2022917
- Higashi H, Masaki S, Kibune M, et al. A 5-6.4- Gb/s 12-channel transceiver with pre-emphasis and equalization [J]. IEEE Journal of Solid-State Circuits, 2005, 40(4): 978-985 https://doi.org/10.1109/JSSC.2005.845562
- Kim J. A four-channel 3.125-Gb/s/ch CMOS serial/link transceiver with a mixed/mode adaptive equalizer [J]. IEEE Journal of Solid-State Circuits, 2005, 40(2): 462-471 https://doi.org/10.1109/JSSC.2004.841037
- Takauchi H. A CMOS multichannel 10-Gb/s transceiver [J]. IEEE Journal of Solid-State Circuits, 2003, 38(12): 2094-2100 https://doi.org/10.1109/JSSC.2003.818577
- Lee H R, Hwang M S, Lee B J, et al. A 1.2-V-only 900-mW 10 Gb Ethernet transceiver and XAUI Interface with robust VCO tuning technique [J]. IEEE Journal of Solid-State Circuits, 2005, 40(11): 2148-2158 https://doi.org/10.1109/JSSC.2005.857360
-
Ishihara N, Fujita S, Togashi M, et al. 3.5-Gb/s
${\times}$ 4- Ch Si bipolar LSI's for optical Interconnections [J]. IEEE Journal of Solid-State Circuits, 1995, 30(12): 1493-1501 https://doi.org/10.1109/4.482197 - Fukaishi M, Nakamura K, Heiuchi H, et al. A 20- Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays [J]. IEEE Journal of Solid-State Circuits, 2000, 35(11):1611-1618 https://doi.org/10.1109/4.881206
- Tanaka K, Fukaishi M, Takeuchi M, et al. A 100Gb/s transceiver with GND-VDD commonmode receiver and flexible multi-channel aligner [C]. IEEE Int. Solid-State Circuits Conf. 2002, (2): 264-265
- Landman P, Yee A L, Gu R, et al. A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology [C]. IEEE ISSCC Dig. Tech. Papers, 2002, (2): 52-53
- Miki Y. A 50-mW/ch 2.5/Gb/s/ch data recovery circuit for SFI-5 interface with digital eye-tracking [J]. IEEE Journal of Solid-State Circuits, 2004, 39(4): 613-621 https://doi.org/10.1109/JSSC.2004.824704
- Kromer C, Sialm G, Menolfi C, et al. A 25-Gb/s CDR in 90-nm CMOS for high-density interconnects [J]. IEEE Journal of Solid-State Circuits, 41(12): 2921-2929
- Zhang D, Jin X, Cheung E, et al. A quad 3.125 Gb/s/channel transceiver with analog phase rotators [C]. IEEE ISSCC Dig. Tech. Papers, 2002, (2):70-71
- Yang F, O'Neill J H, Inglis D, et al. A CMOS lowpower multiple 2.5-3.125-Gb/s serial link macrocell for high IO bandwidth network ICs [J]. IEEE Journal of Solid-State Circuits, 2002, 37(12): 1813- 1821 https://doi.org/10.1109/JSSC.2002.804341
- Yang F, O'Nerill J, Larsson P, et al. A 1.5V 86mW/ch 8-Channel 622-3125Mb/s/ch CMOS SerDes Macrocell with selectable Mux/Demux Ratio [C]. IEEE ISSCC, Dig. Tech. Papers, 2002, 1: 68-69
- Moon Y. A quad 0.6/3.2 Gb/s/channel interferencefree CMOS transceiver for backplane serial link [J]. IEEE Journal Solid-State Circuits, 2004, 39(5): 795-803 https://doi.org/10.1109/JSSC.2004.826311
-
Kaeriyama S, Mizuno M. A 10 Gb/s/ch 50 mW 120
${\times}$ $120{\mu}m^{2}$ clock and data recovery circuit [C]. IEEE Int. Solid State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2003, (2): 70-71 - Lee K H, Kim S J, Ahn G J, et al. A CMOS serial link for fully deplexed data communication [J]. IEEE Journal of Solid-State Circuits, 1995, 30(4): 353-364 https://doi.org/10.1109/4.375953
-
Kim S, Lee K, Jeong D K, et al. An 800 Mbps multi-channel CMOS serial link with 3
${\times}$ oversampling [C]. Proc. IEEE Custom Integrated Circuits Conf., 1995, (5): 451-454 - David G M. Synchronization in digital system design [J]. IEEE Journal of Selected Areas in Communications, 1990, 8(8):1404-1419 https://doi.org/10.1109/49.62819
- Alioto M, Palumbo G. Model and Design of Bipolar and MOS Current-mode Logic: CML, ECL and SCL Digital Circuits [M]. The Netherlands:Springer, 2005
- Rein H M, Moller M. Design considerations for very-high-speed Si bipolar IC's operating up to 50 Gb/s [J]. IEEE Journal of Solid-State Circuits, 1996, 31(8):1076-1090 https://doi.org/10.1109/4.508255
- Pottbäcker A, Langman U, Schreiber H U. A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s [J]. IEEE Journal of Solid- State Circuits, 1992, 27(12): 1747-1751 https://doi.org/10.1109/4.173101
- Savoj J, Razavi B. A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector [J]. IEEE Journal of Solid-State Circuits, 2003, 38 (1): 13-21 https://doi.org/10.1109/JSSC.2002.806284
- Razavi B. Design of integrated circuits for optical communications [M]. New York: McGraw -Hill, 2003: 197-200
피인용 문헌
- Effect of PVT variations on differential-time signaling data link architecture pp.1573-1979, 2018, https://doi.org/10.1007/s10470-018-1304-4