DOI QR코드

DOI QR Code

The Optimal Design of Junctionless Transistors with Double-Gate Structure for reducing the Effect of Band-to-Band Tunneling

  • Wu, Meile (School of Information Science and Engineering, Shenyang University of Technology) ;
  • Jin, Xiaoshi (School of Information Science and Engineering, Shenyang University of Technology) ;
  • Kwon, Hyuck-In (School of Electrical and Electronics Engineering, Chung-Ang University) ;
  • Chuai, Rongyan (School of Information Science and Engineering, Shenyang University of Technology) ;
  • Liu, Xi (School of Information Science and Engineering, Shenyang University of Technology) ;
  • Lee, Jong-Ho (School of EECS Eng. and ISRC (Inter-University Semiconductor Research Center), Seoul National University)
  • Received : 2012.12.03
  • Accepted : 2013.01.28
  • Published : 2013.06.30

Abstract

The effect of band-to-band tunneling (BTBT) leads to an obvious increase of the leakage current of junctionless (JL) transistors in the OFF state. In this paper, we propose an effective method to decline the influence of BTBT with the example of n-type double gate (DG) JL metal-oxide-semiconductor field-effect transistors (MOSFETs). The leakage current is restrained by changing the geometrical shape and the physical dimension of the gate of the device. The optimal design of the JL MOSFET is indicated for reducing the effect of BTBT through simulation and analysis.

Keywords

References

  1. Jean-Pierre Colinge, Chi-Woo Lee, Aryan Afzalian, et al. Nanowire transistors without junctions. Nat. Nanotechnology, 2010, 5 (3): 225-229. https://doi.org/10.1038/nnano.2010.15
  2. Suresh Gundapaneni, Mohit Bajaj,Rajan K. Pajan, et al.Effect of band- to-band tunneling on junctionless transistors. IEEE Transactions on Electron Devices, 2012, 59 (4) : 1023-1029. https://doi.org/10.1109/TED.2012.2185800
  3. Elena Gnani, Antonio Gnudi, Susanna Reggiani, et al. Theory of the junctionless nanowire FET. IEEE Transactions on Electron Devices, 2011, 58 (9): 2903-2910. https://doi.org/10.1109/TED.2011.2159608
  4. E. Gnani, A. Gnudi, S. Reggiani, et al. Numerical investigation on the junctionless nanowire FET. Solid-State Electronic, 2012, 71: 13-18. https://doi.org/10.1016/j.sse.2011.10.013
  5. Manuel Aldegunde, Antonio Martinez, John R. Barker, et al. Study of discrete doping-induced variability in junctionless nanowire MOSFETs using dissipative quantum transport simulations. IEEE Electron Device Letters, 2012, 33 (2): 194- 196. https://doi.org/10.1109/LED.2011.2177634
  6. Greg Leung, Chi On Chui. Variability impact of random dopant fluctuation on nanoscale junctionless FinFETs. IEEE Electron Device Letters, 2012, 33 (6): 767-769. https://doi.org/10.1109/LED.2012.2191931
  7. Elena Gnani, Antonio Gnudi, Susanna Reggiani, et al. Physical model of the junctionless utb soi-fet. Science of Advanced Materials, 2011, 3 (3): 477- 482. https://doi.org/10.1166/sam.2011.1163
  8. Jean-Michel Sallese, Nicolas Chevillon, Christophe Lallement, et al. Charge-Based Modeling of Junctionless Double-Gate Field-Effect Transistors. IEEE Transactions on Electron Devices, 2011, 58 (8): 2628-2636. https://doi.org/10.1109/TED.2011.2156413
  9. SILVACO International. ATLAS User's Manual, 2005.

Cited by

  1. Tunneling field-effect transistor with Si/SiGe material for high current drivability vol.53, pp.6S, 2014, https://doi.org/10.7567/JJAP.53.06JE12
  2. A novel high performance junctionless FETs with saddle-gate vol.14, pp.3, 2015, https://doi.org/10.1007/s10825-015-0702-4
  3. Development of Gate Structure in Junctionless Double Gate Field Effect Transistors vol.19, pp.4, 2015, https://doi.org/10.7471/ikeee.2015.19.4.514
  4. High-Speed Low-Power Junctionless Field-Effect Transistor with Ultra-Thin Poly-Si Channel for Sub-10-nm Technology Node vol.16, pp.2, 2016, https://doi.org/10.5573/JSTS.2016.16.2.159
  5. A novel high-performance H-gate U-channel junctionless FET vol.16, pp.2, 2017, https://doi.org/10.1007/s10825-017-0966-y
  6. An analytical drain current model for cylindrical gate DMG-GC-DOT MOSFET pp.2168-1732, 2018, https://doi.org/10.1080/21681724.2018.1540058
  7. A novel low leakage saddle junctionless FET with assistant gate pp.08943370, 2018, https://doi.org/10.1002/jnm.2465