JSTS:Journal of Semiconductor Technology and Science

  • 제13권2호
  • /
  • Pages.152-156
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  • 2013
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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A 0.5-2.0 GHz Dual-Loop SAR-controlled Duty-Cycle Corrector Using a Mixed Search Algorithm

  • Han, Sangwoo (Electronic and Electrical Engineering, Hongik University) ;
  • Kim, Jongsun (Electronic and Electrical Engineering, Hongik University)
  • 투고 : 2012.08.20
  • 심사 : 2012.11.07
  • 발행 : 2013.04.30
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초록

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

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참고문헌

  1. S. K. Kao and S. I. Liu, "All-Digital Fast-Locked Synchronous Duty-Cycle Corrector," IEEE Trans. on Circuits and Systems, Vol. 53, pp. 1363-1367, 2006.
  2. B. Kim, K. Oh, L. Kim, and D. Lee "A 500MHz DLL with Second Order Duty Cycle Corrector for Low Jitter," IEEE Custom Integrated Circuits Conference, pp. 325-328, 2005.
  3. J. C. Ha, J. H. Lim, Y. J. Kim, W. Y. Jung, J. K. Wee, "Unified all-digital duty cycle and phase correction circuit for QDR I/O interface," IET Electronics Letters, pp. 1300-1301, 2008.
  4. S. Han and J. Kim, "Hybrid duty-cycle corrector circuit with dual feedback loop," IET Electronics Letters, Vo. 47, No. 24, pp. 1311-1313, 2011. https://doi.org/10.1049/el.2011.2710
  5. Y. Min, C. Jeong, K. Kim, W. Choi, J. Son, C. Kim, and S. Kim, "A 0.31-1 GHz fast-corrected dutycycle corrector with successive approximation register for DDR DRAM applications," IEEE Trans. on VLSI Systems, Vol. 20, pp. 1524-1528, 2012. https://doi.org/10.1109/TVLSI.2011.2158011
  6. G. Dehng, J. Hsu, C. Yang, and S. Liu, "Clockdeskew buffer using a SAR-controlled delay-locked loop," IEEE J. Solid-State Circuits, Vol. 35, No. 8, pp. 1128-1136, 2000. https://doi.org/10.1109/4.859501
  7. Sangwoo Han and Jongsun Kim, "Design of high performance CMOS hybrid duty-cycle corrector circuit," 2012 SoC conference, A13, 2012.