JSTS:Journal of Semiconductor Technology and Science

  • 제13권2호
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  • Pages.145-151
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  • 2013
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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A Low Power, Small Area Cyclic Time-to-Digital Converter in All-Digital PLL for DVB-S2 Application

  • Kim, Hongjin (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, SoYoung (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Kang-Yoon (College of Information and Communication Engineering, Sungkyunkwan University)
  • 투고 : 2012.08.09
  • 심사 : 2012.11.29
  • 발행 : 2013.04.30
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초록

In this paper, a low power, small area cyclic time-to-digital converter in All-Digital PLL for DVB-S2 application is presented. Coarse and fine TDC stages in the two-step TDC are shared to reduce the area and the current consumption maintaining the resolution since the area of the TDC is dominant in the ADPLL. It is implemented in a 0.13 ${\mu}m$ CMOS process with a die area of 0.12 $mm^2$. The power consumption is 2.4 mW at a 1.2 V supply voltage. Furthermore, the resolution and input frequency of the TDC are 5 ps and 25 MHz, respectively.

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참고문헌

  1. R. B. Staszewski, P. T. Balsara, "Phase-domain alldigital phase-locked loop," IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 52, no. 3, pp. 159-163, Mar. 2005. https://doi.org/10.1109/TCSII.2004.842067
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  6. Minjae Lee, M. E. Heidari, A. A. Abidi, "A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse-Fine Time-to-Digital Converter With Subpicosecond Resolution," IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2808-2816, Oct. 2009. https://doi.org/10.1109/JSSC.2009.2028753
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피인용 문헌

  1. The Design of a 0.15 ps High Resolution Time-to-Digital Converter vol.15, pp.3, 2015, https://doi.org/10.5573/JSTS.2015.15.3.334
  2. A Study on the Noise Improvement of All Digital Phase-Locked Loop Using Time-to-Digital Converter vol.52, pp.2, 2015, https://doi.org/10.5573/ieie.2015.52.2.195