Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
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Warpage Characteristics of Bottom Packages for Package-on-Package(PoP) with Different Chip Mounting Processes

칩 실장공정에 따른 Package on Package(PoP)용 하부 패키지의 Warpage 특성

  • Jung, D.M. (Department of Materials Science and Engineering, Hongik University) ;
  • Kim, M.Y. (Department of Materials Science and Engineering, Hongik University) ;
  • Oh, T.S. (Department of Materials Science and Engineering, Hongik University)
  • 정동명 (홍익대학교 공과대학 신소재공학과) ;
  • 김민영 (홍익대학교 공과대학 신소재공학과) ;
  • 오태성 (홍익대학교 공과대학 신소재공학과)
  • Received : 2013.09.13
  • Accepted : 2013.09.27
  • Published : 2013.09.30
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Abstract

The warpage of a bottom package of Package on Package(PoP) where a chip was mounted to a substrate by flip chip process was compared to that of a bottom package for which a chip was bonded to a substrate using die attach film(DAF). At the solder reflow temperature of $260^{\circ}C$, the packages processed with flip chip bonding and DAF bonding exhibited warpages of $57{\mu}m$ and $-102{\mu}m$, respectively. At the temperature range between room temperature and $260^{\circ}C$, the packages processed with flip chip bonding and DAF bonding exhibited warpage values ranging from $-27{\mu}m$ to $60{\mu}m$ and from $-50{\mu}m$ to $-15{\mu}m$, respectively.

Package on Package(PoP)용 하부 패키지에 대해 플립칩 본딩으로 칩을 기판에 실장한 패키지와 die attach film(DAF)을 사용하여 칩을 기판에 접착한 패키지의 warpage 특성을 비교하였다. 플립칩 본딩으로 칩을 기판에 실장한 패키지와 DAF를 사용하여 칩을 기판에 실장한 패키지는 솔더 리플로우 온도인 $260^{\circ}C$에서 각기 $57{\mu}m$와 $-102{\mu}m$의 warpage를 나타내었다. 상온에서 $260^{\circ}C$ 사이의 온도 범위에서 플립칩 실장한 패키지는 $-27{\sim}60{\mu}m$ 범위의 warpage를 나타내는 반면에, DAF 실장한 패키지는 $-50{\sim}-153{\mu}m$ 범위의 warpage를 나타내었다.

Keywords

References

  1. J. B. Kim, S. H. Kim and Y. B. Park, "Intermetallic Compound Growth Characteristics of Cu/Ni/Au/Sn-Ag/Cu Microbump for 3-D IC Packages", J. Microelectron. Packag. Soc., 20(2), 59 (2013).
  2. Y. H. Cho, S. E. Kim and S. Kim, "Wafer Level Bonding Technology for 3D Stacked IC", J. Microelectron. Packag. Soc., 20(1), 7 (2013). https://doi.org/10.6117/kmeps.2013.20.1.007
  3. M. J. Yim, R. Strode, R. Adimula and C. Yoo, "Effects of Material Properties on PoP Top Package Warpage Behaviors", Proc. 60th Electronic Components and Technology Conference (ECTC), Las Vegas, 1071, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2010).
  4. M. Amagi and Y. Suzuki, "A Study of Package Warpage for Package on Package (PoP)", Proc. 60th Electronic Components and Technology Conference (ECTC), Las Vegas, 226, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2010).
  5. N. Vijayaragavan, F. Carson and A. Mistry, "Package on Package Warpage - Impact on Surface Mount Yields and Board Level Reliability", Proc. 58th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 389, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2008).
  6. M. J. Yim, R. Strode, R. Adimula, J. J. Zhang and C. Yoo, "Ultra Thin Top Package using Compression Mold: Its Warpage Control", Proc. Proc. 61st Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 1141, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2011).
  7. J. Zhao, Y. Luo, Z. Huang and R. Ma, "Effects of Package Design on Top PoP Package Warpage", Proc. 58th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 1081, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2008).
  8. K. Y. Lee, T. Oh, J. H. Lee and T. S. Oh, "Electrical Characteristics of the Three-Dimensional Interconnection Structure for the Chip Stack Package with Cu through Vias", J. Electron. Mater., 36, 123 (2007). https://doi.org/10.1007/s11664-006-0020-5
  9. Y. K. Jee, J. Yu, K. W. Park, and T. S. Oh, "Zinc and Tin- Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package", J. Electron. Mater., 38, 685 (2009). https://doi.org/10.1007/s11664-008-0646-6
  10. F. Carson, S. M. Lee and N. Vijayaragavan, "Controlling Top Package Warpage for PoP Applications", Proc. 57th Electronic Components and Technology Conference (ECTC), Reno, 737, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2007).
  11. F. Liu, C. T. Yao, D. S. Jiang, Y. P. Wang and C. S. Hsiao, "Halogen-Free Mold Compound Development for Ultra-Thin Packages", Proc. 57th Electronic Components and Technology Conference (ECTC), Reno, 1051, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2007).
  12. B. H. Lee, M. K. Kim and J. W. Joo, "Thermo-mechanical Behavior of WL-PBGA Packages with Pb-Sn Solder and Lead-free Solder Using Moire Interferometry", J. Microelectron. Packag. Soc., 17, 17 (2010).
  13. JEDEC Standard JESD22-B112A, "Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature", JEDEC Solid State Technology Association, Arlington (2009).

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