Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
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Effects of Wafer Warpage on the Misalignment in Wafer Level Stacking Process

웨이퍼 레벨 적층 공정에서 웨이퍼 휘어짐이 정렬 오차에 미치는 영향

  • Shin, Sowon (Microsystem Packaging Center, Seoul Technopark) ;
  • Park, Mansoek (Microsystem Packaging Center, Seoul Technopark) ;
  • Kim, Sarah Eunkyung (Graduate School of NID Fusion Technology, Seoul National University of Science and Technology) ;
  • Kim, Sungdong (Dept. of Mechanical System Design Eng., Seoul National University of Science and Technology)
  • 신소원 (서울테크노파크 MSP 기술지원센터) ;
  • 박만석 (서울테크노파크 MSP 기술지원센터) ;
  • 김사라은경 (서울과학기술대학교 NID 융합기술대학원) ;
  • 김성동 (서울과학기술대학교 기계시스템디자인공학과)
  • Received : 2013.09.05
  • Accepted : 2013.09.25
  • Published : 2013.09.30
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Abstract

In this study, the effects of wafer warpage on the misalignment during wafer stacking process were investigated. The wafer with $45{\mu}m$ bow height warpage was purposely fabricated by depositing Cu thin film on a silicon wafer and the bonding misalignment after bonding was observed to range from $6{\mu}m$ to $15{\mu}m$. This misalignment could be explained by a combination of $5{\mu}m$ radial expansion and $10{\mu}m$ linear slip. The wafer warpage seemed to be responsible for the slip-induced misalignment instead of radial expansion misalignment.

본 연구에서는 웨이퍼 레벨 적층 과정에서 발생하는 웨이퍼 오정렬(misalignment) 현상과 웨이퍼 휘어짐(warpage)과의 관계에 대해서 조사하였다. $0.5{\mu}m$ 두께의 구리 박막 증착을 통해 최대 $45{\mu}m$의 휨 크기(bow height)를 갖는 웨이퍼를 제작하였으며, 이 휘어진 웨이퍼와 일반 웨이퍼를 본딩하였을 때 $6{\sim}15{\mu}m$ 정도의 정렬 오차가 발생하였다. 이는 약 $5{\mu}m$의 웨이퍼 확장(expansion)과 약 $10{\mu}m$의 미끄러짐(slip)의 복합 거동으로 설명할 수 있으며, 웨이퍼 휘어짐의 경우 확장 오정렬보다 본딩 과정에서의 미끄러짐 오정렬에 주로 기여하는 것으로 보인다.

Keywords

References

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Cited by

  1. Wafer level Cu–Cu direct bonding for 3D integration vol.137, 2015, https://doi.org/10.1016/j.mee.2014.12.012
  2. 유한요소 해석을 이용한 팬아웃 웨이퍼 레벨 패키지 과정에서의 휨 현상 분석 vol.25, pp.1, 2018, https://doi.org/10.6117/kmeps.2018.25.1.041