JSTS:Journal of Semiconductor Technology and Science

  • 제12권3호
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  • Pages.341-352
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  • 2012
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Energy Efficient Processing Engine in LDPC Application with High-Speed Charge Recovery Logic

  • Zhang, Yimeng (Graduate School of Information, Production and Systems, Waseda University) ;
  • Huang, Mengshu (Graduate School of Information, Production and Systems, Waseda University) ;
  • Wang, Nan (Graduate School of Information, Production and Systems, Waseda University) ;
  • Goto, Satoshi (Graduate School of Information, Production and Systems, Waseda University) ;
  • Yoshihara, Tsutomu (Graduate School of Information, Production and Systems, Waseda University)
  • 투고 : 2011.12.28
  • 발행 : 2012.09.30
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초록

This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven and low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce operating power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18 2m CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1 pJ/cycle when working at the frequency of 403 MHz, which is only 36% of PE with the conventional static CMOS gates. The measurement results show that the test chip can work as high as 609 MHz with the energy dissipation of 2.1 pJ/cycle.

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참고문헌

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