참고문헌
- Hitachi, Ltd., Matsushita Electric Industrial Co., Ltd.Philips Consumer Electronics, International B.V., Silicon Image, Inc., Sony Corporation, Thomson Inc., Toshiba Corporation, "High-Definition Multimedia Interface Specification," Version 1.3, June 22, 2006
- Digital Display Working Group, "Digital Visual Interface DVI," Revision 1.0, April 1999
- National Semiconductor, "LVDS owner's manual, " 3rd Edition, Spring 2004
- Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, NEC, Philips, "Universal Serial Bus Specification," Revision 2.0, April 27, 2000
- VESA, VESA DispalyPort Standard, Version 1, Revision 1a, January 11, 2008
- VESA, VESA DisplayPort Standard, Version 1, Revision 2, January 5, 2010
- VESA, DisplayPort Link Layer Compliance Test Standard, Version 1.0, September 14, 2007
- Yoo-woo Kim, Seong-bok Cha, and Jin-Ku, "A Design of DisplayPort Link Layer," International SoC Design Conference, pp. 45-48, November, 2008
- Seong-bok Cha, Yong-woo Kim, and Jin-Ku Kang, "A Design of DisplayPort AUX Channel," SoC Conference, Jeonju, Korea, May 2009
- A. X. widmer, "A DC-balanced, Partitioned-Block, 8B/10B Transmission Code," IBM J. Res. Develop, vol.27 pp. 440-451, September 1983 https://doi.org/10.1147/rd.275.0440
- ARM, AMBA Specification, Rev 2.0, 1999
- A. Bystrov, D.J .Kinniment and A. Yakovlev, "Priority Arbiters", in Proc. IEEE 6th international Symp. ASYNC, pp.128-137, April. 2000
- Mary K. Vernon and U. Manber, "Distributed Round-Robin and First-come First-Serve Protocols and Their Application to Multiprocessor Bus Arbitration", The ACM 15th Annual International Symposium on Computer Architecture, 1988
- Y. Xu, L. Li, Ming-lun Gao, B.Zhand, Zhao-yu Jiand, Gao-ming Du and W.Zhang, "An Adaptive Dynamic Arbiter for Multi-Processor SoC", Solid-State and Integrated Circuit Technology International Conf., pp.1993-1996, 2006
- S.Shimizu, T.Matsuoka, and K.Taniguchi, "Parallel bus systems using code-division multiple access technique",in Proc. IEEE Int. Symp. Circuits Syst., pp.II-240-II-243, 2003
- K. Lahiri, A. Raghunathan and G. Lakshminarayana, "The LOTTERY BUS On-Chip Communication Architecture",IEEE Trans. VLSI Systems, vol.14, no.6, 2006
- K. Kim, S. Lee, K. Lee, and H. Yoo, "an arbitration look-ahead scheme for reducing end-to-end latency in networks on chip,"IEEE Circuits and Systems, pp.2357-360, 2005