마이크로전자및패키징학회지 (Journal of the Microelectronics and Packaging Society)

  • 제18권4호
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  • Pages.49-53
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  • 2011
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  • 1226-9360(pISSN)
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  • 2287-7525(eISSN)
한국마이크로전자및패키징학회 (The Korean Microelectronics and Packaging Society)
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3차원 실장용 TSV 고속 Cu 충전 및 Non-PR 범핑

High-Speed Cu Filling into TSV and Non-PR Bumping for 3D Chip Packaging

  • 홍성철 (서울시립대학교 신소재공학과) ;
  • 김원중 (서울시립대학교 신소재공학과) ;
  • 정재필 (서울시립대학교 신소재공학과)
  • 투고 : 2011.12.14
  • 심사 : 2011.12.22
  • 발행 : 2011.12.30
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초록

TSV(through-silicon-via)를 이용한 3차원 Si 칩 패키징 공정 중 전기 도금을 이용한 비아 홀 내 Cu 고속 충전과 범핑 공정 단순화에 관하여 연구하였다. DRIE(deep reactive ion etching)법을 이용하여 TSV를 제조하였으며, 비아홀 내벽에 $SiO_2$, Ti 및 Au 기능 박막층을 형성하였다. 전도성 금속 충전에서는 비아 홀 내 Cu 충전율을 향상시키기 위하여 PPR(periodic-pulse-reverse) 전류 파형을 인가하였으며, 범프 형성 공정에서는 리소그라피(lithography) 공정을 사용하지 않는 non-PR 범핑법으로 Sn-3.5Ag 범프를 형성하였다. 전기 도금 후, 충전된 비아의 단면 및 범프의 외형을 FESEM(field emission scanning electron microscopy)으로 관찰하였다. 그 결과, Cu 충전에서는 -9.66 $mA/cm^2$의 전류밀도에서 60분간의 도금으로 비아 입구의 도금층 과성장에 의한 결함이 발생하였고, -7.71 $mA/cm^2$에서는 비아의 중간 부분에서의 도금층 과성장에 의한 결함이 발생하였다. 또한 결함이 생성된 Cu 충전물 위에 전기 도금을 이용하여 범프를 형성한 결과, 범프의 모양이 불규칙하고, 균일도가 감소함을 나타내었다.

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.

키워드

참고문헌

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피인용 문헌

  1. Three-Dimesnional Semicondoctor Stacking using TSV(Through-Si-Via) Technology vol.39, pp.3, 2011, https://doi.org/10.5781/jwj.2021.39.3.8
  2. A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process vol.11, pp.10, 2021, https://doi.org/10.3390/met11101664