한국생산제조학회지 (Journal of the Korean Society of Manufacturing Technology Engineers)

  • 제20권5호
  • /
  • Pages.559-563
  • /
  • 2011
  • /
  • 2508-5093(pISSN)
  • /
  • 2508-5107(eISSN)
한국생산제조학회 (The Korean Society of Manufacturing Technology Engineers)
권호 표지

플립칩의 매개변수 변화에 따른 보드레벨의 동적신뢰성평가

Dynamic Reliability of Board Level by Changing the Design Parameters of Flip Chips

  • 김성걸 (서울과학기술대학교 기계설계자동화공학부) ;
  • 임은모 (서울과학기술대학교 기계설계자동차공학부)
  • 투고 : 2011.08.01
  • 심사 : 2011.08.31
  • 발행 : 2011.10.15
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초록

Drop impact reliability assessment of solder joints on the flip chip is one of the critical issues for micro system packaging. Our previous researches have been showing that new solder ball compositions of Sn-3.0Ag-0.5Cu has better mechanical reliability than Sn-1.0Ag-0.5Cu. In this paper, dynamic reliability analysis using Finite Element Analysis (FEA) is carried out to assess the factors affecting flip chip in drop simulation. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard including 15 chips, solder balls and PCB are modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. It is found that larger chip size, smaller chip array, smaller ball diameter, larger pitch, and larger chip thickness have bad effect on maximum yield stress and strain at solder ball of each chip.

키워드

참고문헌

  1. Tee, Y., Luan, J., Ng, H. S., Lim, C. K., Pek, E., and Zhong, Z., 2004, "Advanced Experimental and Simulation Techniques for Analysis of Dynamic Responses during Drop Impact," 54th Electronic Components and Technology Conference, pp. 1088-1094.
  2. Mattila, T. T., Marjamaki, P., and Kivilahti, J. K., 2006, "Reliability of CSP Interconnctions under Mechanical Shock Loading Conditions," IEEE Transaction on Components and Packaging Technologies, Vol. 29, No. 4, pp. 787-795.
  3. Kim, S. K., Kim, H. J., Lim, S. Y., Kim, S. Y., Yang, I. Y., and An, E. J., 2010, "Dynamic Reliability Assesment of Solder Balls on the Design Parameters of Flip Chips," KSMTE Fall Conference, pp. 149-153.
  4. JEDEC standard, 2003, Board Level Drop Test Method of Components for Handheld Electronic Products, JESD22-B111, JEDEC Solid State Technology Association, Electronic Industries Alliance, USA.
  5. Kim, S. K., Kim, K. L., Bae, J. G., Park, S. H., and Lee, D. G., 2009, "Dynamic Analysis of Flip Chips with Solder Balls with Two Different Compositions," KSPE Fall Conference, pp. 207-208.
  6. Kim, S. K., 2011, "Board-Level Drop Analyses having the Flip Chips with Solder balls of Sn-3.0Ag-0.5Cu and Sn-1.0Ag-0.5Cu," J. of the KSMTE, Vol. 20, No. 2, pp. 193-201.
  7. Cai, C., Zheng, h., Khan M. S., and Hung, K. C., 2002, "Modeling of Material Damping Properties in ANSYS," CADFEM Users' Meeting & ANSYS Conference, pp. 9 -24.