한국정보통신학회논문지 (Journal of the Korea Institute of Information and Communication Engineering)

  • 제15권11호
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  • Pages.2465-2473
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  • 2011
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  • 2234-4772(pISSN)
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  • 2288-4165(eISSN)
한국정보통신학회 (The Korea Institute of Information and Commucation Engineering)
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Sign-magnitude 수체계 기반의 WiMAX용 다중모드 LDPC 복호기 설계

A Design of Sign-magnitude based Multi-mode LDPC Decoder for WiMAX

  • 서진호 (금오공과대학교 전자공학부) ;
  • 박해원 (금오공과대학교 전자공학부) ;
  • 신경욱 (금오공과대학교 전자공학부)
  • 투고 : 2011.10.28
  • 심사 : 2011.10.28
  • 발행 : 2011.11.30
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초록

WiMAX, WLAN 등의 무선통신 시스템에 사용되는 LDPC(low density parity check) 복호기의 핵심 기능블록인 DFU(decoding function unit)의 회로 최적화를 제안한다. DFU를 2의 보수 연산 대신에 sign-magnitude 연산 기반으로 설계함으로써 수체계 변환과정을 제거하였으며, 모바일 WiMAX용 다중모드 LDPC 복호기에 사용되는 96개 DFU 배열의 게이트 수를 18% 감소시켰다. 제안된 DFU 구조를 적용하여 모바일 WiMAX 표준을 지원하는 다중모드 LDPC 복호기를 설계하였다. 설계된 LDPC 복호기는 0.18-${\mu}m$ CMOS 셀 라이브러리를 이용하여 50 MHz 클록주파수로 합성한 결과 268,870 게이트와 71,424 비트의 메모리로 구현되었으며, FPGA 구현을 통해 하드웨어 동작을 검증 하였다.

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems including WiMAX and WLAN. A new design of DFU based on sign-magnitude arithmetic instead of two's complement arithmetic is proposed, resulting in 18% reduction of gate count for 96 DFUs array used in mobile WiMAX LDPC decoder. A multi-mode LDPC decoder for mobile WiMAX standard is designed using the proposed DFU. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 50 MHz clock has 268,870 gates and 71,424 bits RAM, and it is verified by FPGA implementation.

키워드

참고문헌

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피인용 문헌

  1. LDPC Decoder for WiMAX/WLAN using Improved Normalized Min-Sum Algorithm vol.18, pp.4, 2014, https://doi.org/10.6109/jkiice.2014.18.4.876
  2. WiMAX/WLAN용 다중표준 LDPC 복호기 설계 vol.17, pp.2, 2011, https://doi.org/10.6109/jkiice.2013.17.2.363