한국정밀공학회지 (Journal of the Korean Society for Precision Engineering)

  • 제27권2호
  • /
  • Pages.13-19
  • /
  • 2010
  • /
  • 1225-9071(pISSN)
  • /
  • 2287-8769(eISSN)
한국정밀공학회 (Korean Society for Precision Engineering)
권호 표지

나노초 펄스 레이저 응용 사파이어/실리콘 웨이퍼 미세 드릴링

Laser Micro-drilling of Sapphire/silicon Wafer using Nano-second Pulsed Laser

  • 김남성 ((주)이오테크닉스 레이저 응용 연구소) ;
  • 정영대 ((주)이오테크닉스 레이저 응용 연구소) ;
  • 성천야 ((주)이오테크닉스 레이저 응용 연구소)
  • 발행 : 2010.02.01
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초록

Due to the rapid spread of mobile handheld devices, industrial demands for micro-scale holes with a diameter of even smaller than $10{\mu}m$ in sapphire/silicon wafers have been increasing. Holes in sapphire wafers are for heat dissipation from LEDs; and those in silicon wafers for interlayer communication in three-dimensional integrated circuit (IC). We have developed a sapphire wafer driller equipped with a 532nm laser in which a cooling chuck is employed to minimize local heat accumulation in wafer. Through the optimization of process parameters (pulse energy, repetition rate, number of pulses), quality holes with a diameter of $30{\mu}m$ and a depth of $100{\mu}m$ can be drilled at a rate of 30holes/sec. We also have developed a silicon wafer driller equipped with a 355nm laser. It is able to drill quality through-holes of $15{\mu}m$ in diameter and $150{\mu}m$ in depth at a rate of 100holes/sec.

키워드

참고문헌

  1. Korea Institute of Science and Technology Information, "LED Technical Trend Report," pp. 6-11, 2007
  2. Terrill, R. and Beene, G. L., "3D packaging technology overview and mass memory applications," IEEE Proc. of Aerospace Applications Conference, Vol. 2, pp. 347-355, 1996.
  3. Campbell, M. L., Toborg, S. T. and Taylor, S. L., "3D wafer stack neurocomputing," Fifth Annual IEEE International Conference on Wafer Scale Integration, pp. 67-74, 1993.
  4. Bertagnolli, E., Bollmann, D., Braun, R., Buchner, R., Engelhardt, M., Grassl, T., Hieber, K., Kawala, G., Kleiner, M., Klumpp, A., Kuhn, S., Landesberger, C., Pamler, W., Popp, R., Ramm, P., Renner, E., Ruhl, G., Scheler, U., Schmidt, C., Schwarzl, S., Weber, J. and Sanger, A., "Interchip via technology-three dimensional metallization for vertically integrated circuits," Fourth International Symposium on Semiconductor Wafer Bonding, pp. 509-520, 1997.
  5. Laydevant, J. L., "High Speed Via Drilling for 3D Interconnect Industrialization," Encasit Workshop, 2006.
  6. Hirafune, S., Yamamoto, S., Wada, H., Okanishi, K., Tomita, M., Matsumaru, K. and Suemasu, T., "Packaging Technology for Imager Using Throughhole Interconnections in Si Substrate," 6th IEEE CPMT Conference on High Density Microsystem Design and Packaging, pp. 303-306, 2004.
  7. Bauer, T., "High Density Through Wafer Via Technology," NSTI Nanotech, Vol. 3, pp. 116-119, 2007.
  8. Brennan, N., Callaghan, J., Hannon, M. and Rodin, A., "High-Throughput Laser Percussion Interconnect Microvia Process," WLT-Conference on Lasers in Manufacturing, 2007.