참고문헌
- W. Dally and B. Towles, 'Route Packets, not Wires: On-Chip Interconnection Networks,' in Proc. Design Automation Conf., Las Vegas, NV. pp.684-689, Nov., 2001.
- R. Ho, K. Mai, and M. Horowitz, "The Future of Wires," Proceeding of the IEEE, Vol.89, No.4, pp.490-504, Apr., 2001. https://doi.org/10.1109/5.920580
- R. Ho, K. Mai, and M. Horowitz, "The Future of Wires," Proceeding of the IEEE, Vol.89, No.4, pp.490-504, Apr., 2001. https://doi.org/10.1109/5.920580
- S. Kumar et al, 'A Network on Chip architectures and Design Methodology,' in Proc. ISVLSI, Pittsburgh, PA, pp.117-124, Apr., 2002 https://doi.org/10.1109/ISVLSI.2002.1016885
- D. Sylvester and K. Keotzer, "Getting to the Bottom of Deep Submicron," in Proc. ICCAD, San Jose, CA, pp.203-211, Nov., 1998. https://doi.org/10.1109/ICCAD.1998.742874
- W. Vanderbauwhede and D. Harle, "Architecture, Design, and Modeling of the OPSnet Asynchronous Optical Packet Switching Node," Journal of Lightwave Technology, Vol.23, No.7, pp.2215-2228, July., 2005. https://doi.org/10.1109/JLT.2005.850023
- M. Ali, M. Welzl, and S. Hellebrand, 'A Dynamic Routing mechanism for Network on Chip,' in Proc. IEEE NORCHIP, Oulu, Finland, pp.70-73, Nov., 2005. https://doi.org/10.1109/NORCHP.2005.1596991
- S. Manolache, P. Eles, and Z. Peng, "Buffer Space Optimization with Communication Synthesis and Traffic Shaping for NoCs," in Proc. DATE, Munich, Germany, pp.718-723, Mar., 2006.
- F. Karim, A. Mellan, A. Nguyen, U. Aydonat, and T. Abdelrahman, "A Multilevel Computing Architecture for Embedded Multimedia Applications," IEEE Micro, Vol.24, No.3, pp.56-66, May/June, 2004. https://doi.org/10.1109/MM.2004.1
- W. Kim and S. Hwang, "Design of an Area- Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E91-A, No.11, pp.3297-3303, Nov., 2008. https://doi.org/10.1093/ietfec/e91-a.11.3297
- S. Kumar et al, 'A Network on Chip architectures and Design Methodology,' in Proc. ISVLSI, Pittsburgh, PA, pp.117-124, Apr., 2002. https://doi.org/10.1109/ISVLSI.2002.1016885
- L. Benini and G. De Micheli, 'Network on Chip: A New SoC Paradigm,' IEEE Computer, Vol.35, No.1, pp.70-78, Jan., 2002. https://doi.org/10.1109/2.976921
- L. Benini and G. De Micheli, Networks on Chips: Technology and Tools, Morgan Kaufmann,2006.
- D. Kim, K. Lee, S. Lee, and H. Yoo, 'A Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Network-on-Chip,' in Proc. Int. Symp. Circuit and Systems, pp.2369- 2372, May, 2005.
- X. Chen and et al, 'Leakage Power Modeling and Optimization in Interconnection Networks,' in Proc. Int. Symp. Low Power Electronics and Design, Seoul, pp.90-95, Aug., 2003. https://doi.org/10.1145/871506.871531
- M. Coenen, S. Murali, A. Ruadulescu, K. Goossens, and G. De Micheli, "A Buffer-sizing Algorithm for Networks on Chips Using TDMA and Credit-Based End-to-end Flow Control," in Proc. International Conference on Hardware Software Codesign, Seoul, pp.130-135, Oct., 2006. https://doi.org/10.1145/1176254.1176287
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Synopsys, Design Analyzer
$\texttrademark$ User Guide,Synopsys${\circledR}$ ,June 2002 -
Synopsys, Power Compiler
$\texttrademark$ User Guide, Synopsys${\circledR}$ ,June 2007