Pipeline Structured-Degree Computationless Modified Euclidean Algorithm for RS(23,17) Decoder

RS(23,17) 복호기를 위한 PS-DCME 알고리즘

  • 강성진 (한국기술교육대학교 정보기술공학부) ;
  • 홍대기 (상명대학교 공과대학 정보통신공학과)
  • Published : 2009.02.28

Abstract

In this paper, A pipeline structured-degree computationless modified Euclidean (PS-DCME) algorithm is proposed, which can be used for a RS(23,17) decoder for MB-OFDM system. PS-DCME algorithm requires a state machine instead of the degree computation and comparison circuits, so that the hardware complexity of the decoder can be reduced and high-speed decoder can be implemented. We have implemented a RS(23,17) decoder with PS-DCME using Verilog HDL and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 19,827.

본 논문에서는 MB-OFDM 시스템에서 사용되는 RS(23,17)부호의 복호기에 사용될 수 있는 PS-DCME(Pipeline Structured-Degree Computationless Modified Euclidean) 알고리즘을 제안한다. 제안된 PS-DCME 알고리즘은 다항식의 차수 계산과 차수 비교를 하지 않고 상태(state) 변화만을 이용하여 ME 알고리즘을 수행하기 때문에, 복호기의 하드웨어 복잡도를 줄일 수 있으며, 고속의 RS(Reed-Solomon) 복호기를 구현할 수 있다. Verilog HDL을 사용하여 알고리즘을 구현하였고, 삼성 65nm library를 이용하여 합성한 결과, 400MHz(2.5nsec)에서 timing closure되었기 때문에, 실제 ASIC을 제작했을 경우에 250MHz정도까지는 동작이 보장된다고 볼 수 있으며, gate count는 19,827이다.

Keywords

References

  1. International Standard, ISO/IEC 26907:2007(E), "Information technology - Telecommunications and information exchange between systems - High Rate Ultra Wideband PHY and MAC Standard"
  2. S. B. Wicker, Error Control Systems for Digital Communication and Storage, Englewood Cliffs, NJ, Prentice-Hall, 1995.
  3. H. M. Shao, T. K. Truong, L. J. Deutsch, J. H. Yuen, and I. S. Reed, "A VLSI design of a pipeline Reed-Solomon decoder", IEEE Trans. Comput., vol. C-34, no. 5, pp. 393-403, May 1985. https://doi.org/10.1109/TC.1985.1676579
  4. H. Lee, "Modified Euclidean algorithm block for high-speed Reed-Solomon decoder", Electron. Lett., 37, pp. 903-904, 2001. https://doi.org/10.1049/el:20010628
  5. H. Lee, "High-speed VLSI architecture for parallel Reed-Solomon decoder", IEEE Trans. Very Large Scale (VLSI) Integr. Syst., vol. 11, no. 2, pp. 288-294, Apr. 2003. https://doi.org/10.1109/TVLSI.2003.810782
  6. S. W. Choi, S. S. Choi, H. Lee, "RS decoder architecture for UWB," IEEE ICACT 2006, pp. 805-808, 2006.
  7. J. H. Baek and M. H. SunWoo, "New degree computationless modified Euclid's algorithm and architecture for Reed-Solomon decoder", IEEE Trans. Very Large Integr. (VLSI) Syst., vol. 14, no. 8, pp 915-920, Aug. 2006. https://doi.org/10.1109/TVLSI.2006.878484
  8. D. V. Sarwate and N. R. Shanbhag, "High-speed architecture for Reed-Solomon Decoders," IEEE Trans. on VLSI Systems, vol. 9, no.55, pp. 641-655, Oct., 2001.
  9. J. H. Baek and M. H. SunWoo, "Enhanced degree computationless modified Euclid's algorithm for Reed-Solomon decoders," Electronics Letters, vol. 43, no. 3, pp. 175-176, Feb., 2007. https://doi.org/10.1049/el:20073718
  10. S. Lee, H. Lee, J. Shin, J. Ko, "A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed- Solomon Decoders," ISCAS, pp. 901-904, May, 2007.