Low-Power 512-Bit EEPROM Designed for UHF RFID Tag Chip

  • Lee, Jae-Hyung (Department of Electronic Engineering, Changwon National University) ;
  • Kim, Ji-Hong (MagnaChip Semiconductor) ;
  • Lim, Gyu-Ho (MagnaChip Semiconductor) ;
  • Kim, Tae-Hoon (Department of Electronic Engineering, Changwon National University) ;
  • Lee, Jung-Hwan (MagnaChip Semiconductor) ;
  • Park, Kyung-Hwan (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Park, Mu-Hun (Department of Electronic Engineering, Changwon National University) ;
  • Ha, Pan-Bong (Department of Electronic Engineering, Changwon National University) ;
  • Kim, Young-Hee (Department of Electronic Engineering, Changwon National University)
  • Received : 2007.05.14
  • Published : 2008.06.30

Abstract

In this paper, the design of a low-power 512-bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low-power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage-up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 ${\mu}m$ EEPROM process. Power dissipation is 32.78 ${\mu}W$ in the read cycle and 78.05 ${\mu}W$ in the write cycle. The layout size is 449.3 ${\mu}m$ ${\times}$ 480.67 ${\mu}m$.

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