대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

Common Subexpression Elimination 회로의 부호 확장 제거

Sign-Extension Reduction Method in Common Subexpression Elimination Circuit

  • 김용은 (전북대학교 전자정보공학부) ;
  • 정진균 (전북대학교 전자정보공학부) ;
  • 이문호 (전북대학교 전자정보공학부)
  • Kim, Yong-Eun (Div. of Electronic & Information Engineering Chonbuk National University) ;
  • Chung, Jin-Gyun (Div. of Electronic & Information Engineering Chonbuk National University) ;
  • Lee, Moon-Ho (Div. of Electronic & Information Engineering Chonbuk National University)
  • 발행 : 2008.09.25
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초록

FIR 필터에서 곱셈기는 대부분의 면적을 차지한다. FIR 필터의 설계시 개별적인 곱셈기 대신 Common Subexpression Elimination(CSE) 알고리즘을 이용하여 덧셈만으로 곱셈기를 구현할 수 있다. CSE방식은 곱셈을 이용하지 않기 때문에 보다 작은 면적으로 필터를 구현할 수 있으나 덧셈에서 발생하는 캐리의 긴 전파 시간으로 인하여 필터 연산시간이 길어지는 단점이 있다. 특히 더해지는 항의 쉬프트가 클수록 부호 확장이 많아지며 부호확장에 의해 덧셈의 면적이 커지고 계산 시간이 길어진다. 본 논문에서는 CSE 알고리즘에서 부호 확장 부분을 제거하는 방법을 제안하며 제안한 알고리즘을 이용하여 주어진 예제를 삼성 0.35u 공정으로 설계하였을 때 기존 설계 방법 보다 면적, 속도, 파워소모에서 각각 17%, 31%, 12% 의 이득이 있음을 보인다.

In FIR filter design, multipliers occupy most of the area. To efficiently reduce the area occupied by multipliers, Common Subexpression Elimination (CSE) algorithm can be used instead of separate multipliers. However, the filter computation time can be increased due to the long carry propagation in CSE circuits. More specifically, when the difference of weights between the two inputs to an adder in CSE circuits is large, long carry propagation time is required due to large sign extension. In this paper, we propose a sign-extension reduction method in common subexpression elimination circuit. By Synopsys simulation using Samsung 0.35um library, it is shown that the proposed method leads to 17%, 31% and 12% reduction in the area, time delay and power consumption, respectively, compared with conventional method.

키워드

참고문헌

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