Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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C-V Characteristics in Nanometer Scale MuGFETs with Considering Quantum Effects

양자 현상을 고려한 나노미터 스케일 MUGFETS의 C-V 특성

  • Yun, Se-Re-Na (Department of Electronics Engineering, University of Incheon) ;
  • Yu, Chong-Gun (Department of Electronics Engineering, University of Incheon) ;
  • Park, Jong-Tae (Department of Electronics Engineering, University of Incheon)
  • Published : 2008.11.25
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Abstract

In this work, a two dimensional, self-consistent Poisson-$Schr{\ddot{o}}dinger$ solver has been implemented to study C-V characteristics in nanometer scale MuGFETs with considering quantum effects. The quantum-mechanical effects on gate-channel capacitance for different device dimension and gate configurations of nanometer scale MuGFETs have been analyzed. It has been found that 4he gate-channel capacitance per unit gate area is increased as the device dimension decreases. For different gate configurations, the gate-channel capacitance is decreased with increase of effective gate number. Those resu1ts have been explained by the distribution profile of electron concentration in the silicon surface and inversion capacitance. The length of inversion-layer centroid has been calculated from inversion capacitance with device dimension and gate configurations.

본 연구에서는 양자 현상을 고려한 나노미터 MuGFET의 C-V 특성을 분석하기 위하여 2차원 Poisson-$Schr{\ddot{o}}dinger$ 방정식을 self-consisnt하게 풀 수 있는 시뮬레이터를 구현하였다. 소자 시뮬레이터를 이용하여 양자 현상으로 인한 소자크기와 게이트 구조에 따른 게이트-채널 커패시턴스 특성을 분석하였다. 소자의 크기가 감소할수록 단위 면적당 게이트-채널 커패시턴스는 증가하였다. 그리고 게이트 구조가 다른 소자에서는 게이트-채널 커패시턴스가 유효게이트 수가 증가할수록 감소하였다. 이런 결과를 실리콘 표면의 전자농도 분포와 인버전 커패시턴스로 설명하였다 또한 인버전 커패시턴스로부터 소자의 크기 및 게이트 구조에 따른 inversion-layer centroid 길이도 계산하였다.

Keywords

References

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