대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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시그마-델타 A/D 컨버터용 디지털 데시메이션 필터 설계

Design of digital decimation filter for sigma-delta A/D converters

  • 변산호 (한양대학교 전자컴퓨터공학) ;
  • 류성영 (한양대학교 전자컴퓨터공학) ;
  • 최영길 (한양대학교 전자컴퓨터공학) ;
  • 노형동 (한양대학교 전자컴퓨터공학) ;
  • 남현석 (한양대학교 전자컴퓨터공학) ;
  • 노정진 (한양대학교 전자컴퓨터공학)
  • Byun, San-Ho (Hanyang University, Dep. of Electrical and Computer Engineering) ;
  • Ryu, Seong-Young (Hanyang University, Dep. of Electrical and Computer Engineering) ;
  • Choi, Young-Kil (Hanyang University, Dep. of Electrical and Computer Engineering) ;
  • Roh, Hyung-Dong (Hanyang University, Dep. of Electrical and Computer Engineering) ;
  • Nam, Hyun-Seok (Hanyang University, Dep. of Electrical and Computer Engineering) ;
  • Roh, Jeong-Jin (Hanyang University, Dep. of Electrical and Computer Engineering)
  • 발행 : 2007.02.25
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초록

오버샘플링(oversampling) 방식의 시그마-델타(sigma-delta) A/D 컨버터에서는 오버샘플링된 신호를 최종 Nyquist rate 으로 낮춰주는 디지털 데시메이션 필터가 필수적이다. 본 논문에서는 면적을 크게 줄이면서 time-to-market의 이점을 가져다주는 고해상도 시그마-델타(sigma-delta) A/D 컨버터용 디지털 데시메이션(decimation) 필터의 Verilog-HDL 설계 및 구현을 보였다. 디지털 데시메이션 필터는 CIC(cascaded integrator-comb) filter와 두 개의 half-band FIR filter로 이루어져 있다. FIR필터에서 곱셈연산의 복잡성을 줄이고 면적을 최소화하기 위해 계수를 CSD(canonical signed digit) 코드로 표현하여 사용하였다. 곱셈 연산은 일반 곱셈기 없이 쉬프트 와 덧셈방식을 이용하여 구현되었다. 3단 데시메이션 필터는 $0.25-{\mu}m$ CMOS 공정으로 제작되었고, 필터의 면적은 $1.36mm^2$ 이며 2.8224 MHz의 클럭 주파수에서 4.4 mW의 파워소모를 보였다. 측정 결과 높은 신호대 잡음 비(SNR)를 요구하는 디지털 오디오용 데시메이션(decimation) 필터의 사양을 충분히 만족시키고 있음을 볼 수 있다.

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

키워드

참고문헌

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