대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

99dB의 DR를 갖는 단일-비트 4차 고성능 델타-시그마 모듈레이터 설계

Design of a 99dB DR single-bit 4th-order High Performance Delta-Sigma Modulator

  • 최영길 (한양대학교 전자컴퓨터공학) ;
  • 노형동 (한양대학교 전자컴퓨터공학) ;
  • 변산호 (한양대학교 전자컴퓨터공학) ;
  • 남현석 (한양대학교 전자컴퓨터공학) ;
  • 노정진 (한양대학교 전자컴퓨터공학)
  • Choi, Young-Kil (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.) ;
  • Roh, Hyung-Dong (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.) ;
  • Byun, San-Ho (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.) ;
  • Nam, Hyun-Seok (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.) ;
  • Roh, Jeong-Jin (Dep. of Electrical Engineering and Computer Science, Hanyang Univ.)
  • 발행 : 2007.02.25
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초록

본 논문에서는 높은 dynamic range(DR)를 얻을 수 있는 단일-비트 4차 델타-시그마 모듈레이터를 제시하였으며, 이를 구현하였다. 본 모듈레이터에 사용된 루프 필터의 구조는 피드백 패스와 피드포워드 패스를 혼합하여 사용한 구조이며, 스위치-커패시터(switched-capacitor) 방식으로 구현되었다. 측정 결과로는 20kHz의 기저대역(base band)에서 3.2MHz의 클록을 사용하였을 때 최대 99dB의 DR을 얻었다. 본 모듈레이터는 $0.18{\mu}m$ standard CMOS 공정으로 만들어졌다.

In this paper, a fourth-order single-bit delta-sigma modulator is presented and implemented. The loop-filter is composed of both feedback and feedforward paths. Measurement results show that maximum 99dB dynamic range is achievable at a clock rate of 3.2MHz for 20kHz baseband. The proposed modulator has been fabricated in a $0.18{\mu}m$ standard CMOS process.

키워드

참고문헌

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