참고문헌
- R.R. Troutman, 'VLSI limitations from drain-induced barrier lowering', IEEE Trans. Electron Devices, v.ED-26, pp. 461, (1979)
- S.G. Chamberlain and S. Ramanan, 'Drain-induced barrier-lowering analysis in VLSI MOSFET devices using two-dimensional numerical simulations', IEEE Trans. Elec. Device. v.ED-33, pp.1745, (1986)
- T. Skotnicki and T.Pedron, 'Anormalous punchthrough in ULSI buried-channel MOSFET's', IEEE Trans. Elec. Device. v.ED-36, pp.2548, (1989)
- M.J. Van der Tol and S.G. Chamberlain, 'Draininduced barrier lowering in buried-channel MOSFET's', IEEE Trans. Electron Devicees v.ED-40, pp. 741, (1993)
- N. Ballay and B. Baylad, 'Analytical modeling of depletion-mode MOSFET with short- and narrowchannel effects', IEE Proc., v. 128, pt. I, no. 6, pp. 225, (1981)
- H. Oka, K. Nishiuchi, T. Nakamura and H. Isgikawa, 'Computer analysis of a short-channel BC MOSFET', IEEE Trans. Elec. Device. v.ED-27, pp. 1514, (1980)
- B.C. Burkey, G. Lubberts, E.A. Trabka and T.J. Tredwell, 'Channel potential and channel width in narrow buried-channel MOSFET's', IEEE Trans. Electron Devices, v.ED-31, pp. 423, (1984)
- M. Carqut, D. Rigaud, A. Touboul and Y. Thenoz, 'A two-dimensional numerical approach to achieve a silicon BCCD cell optimal design', IEEE Trans. Electron Devices, v.ED-35, pp.1445, (1988)
- M.H. Kim and S.H. Lim, Three dimensional numerical simulation of buried-channel MOSFETs, ICEIC 2000 Proceedings of 'The 2000 International Conference on Electronics, Information and Communication', pp. 453, August 9-11, 2000, Shenyang, China
- M.H. Kim, 3-D Characterizing analysis of buriedchannel MOSFETs, Optical Society of Korea Summer Meeting, FA-V21, pp. 162, (2000)
- W. Fichtner, D.J. Rose and R.E. Bank, 'Semiconductor device simulation', IEEE Trans. Electron Devices, v.ED-30, pp. 1018, (1989)
- M.H. Kim, Determination of charge handling capability of a deep depletion charge coupled device based on a three-dimensional numerical simulation, Proceedings, SPIE, v. 2654, Solid State Sensor Arrays and CCD Cameras, 1996, pp. 51, (1996)
- M.H. Kim, 3-D numerical analysis of astronomic CCDs with a deep depletion, Optical Society of Korea Summer Meeting, FA-V21, pp. 228, (2000)
- H-H Li and C-Y Wu, 'A navel extraction technique for the effective channel length of MOSFET devices', IEEE Trans. Electron Devices, v.ED-42, pp. 856, (1995)
- M.H. Kim, Three-dimensional numerical analysis of astronomical CCD image sensors for X-ray or UV detection, Ph. D. Thesis, University of Leicester, UK, (1995)
- J.V. Ashby, C.J. Fitzsimons, R.F. Flowler and C. Greenough, 'The adaptive solution of three-dimensional semiconductor device problems', Proceedings of the Third International Conference on Numerical Grid Generation in Computational Fluid Dynamics and Related Fields, North Holland, pp. 417, (1991)
- J. Bisschop, 'Computer simulation of parallel-to series conversion in solid state frame transfer image sensors', Proc. Int. Conf. on Simulation of Semiconductor of Devices and Process, Bologna, v. 3, pp. 207, (1988)
- A. Husain and S.G. Chamberlain, 'Threedimensional simulation of VLSI MOSFET's: The three-dimensional simulation program WATMOS', IEEE Trans. Electron Devices, v.ED-29, pp. 631, (1982)
피인용 문헌
- $\hbox{VO}_{2}$ Thin-Film Varistor Based on Metal-Insulator Transition vol.31, pp.1, 2010, https://doi.org/10.1109/LED.2009.2034763